In RX71M UHM (section 33.3.2), it says about the protection of WDTCR and WDTRCR:
"The protection is released by the reset source of the WDT. With other reset sources, the protection is not released"
I don't understand this statement. I found that:
1. after the WDT has been refreshed once, and subsequently underflows and generate an NMI, and if user press RES#pin, subsequent writing to the two registers will work
2. after the WDT has been refreshed once, and subsequently underflows and generate an RESET, subsequent writing to the two registers has no effect
Is this how it supposed to work? Does it mean that, the only way to release to protection is by the RES#pin?
In reply to splee:
Hi Splee, Correct me if I'm wrong but as what I've seen in "Figure 33.5 Control Waveforms Produced in Response to Writing to the WDTCR Register", WDTCR and WDTRCR registers write protection is protected by the Register protection signal (which is an internal signal), not by the RES# pin state. As shown in the timing diagram, when the Register protection signal is low, writing to the WDTCR and WDTRCR registers are possible. When the protection signal becomes HIGH, writing is disabled. Honestly, I'm not really familiar with the WDT registers of RX71M but I suggest to read more about the WDT registers in 33.2. As I can see in figure 33.1, the reset is generated by the WDT control circuit, I'm not just sure what specific register controls it. JB RenesasRulz Forum Moderator