RX63N ADC DTC Interrupt at the end of transfer doesn't fire

Hi, I'm new with RX63N platform. I'm trying to setup the ADC with DTC for Normal transfer mode with Interrupt at the end of the transfer. The transfer is ok but the interrupt doesn't fire.

I started the project from the Sample project Flash_BGO of Renesas site. The sample project is setup for repeat mode.

Below there is my modified code: 


/* Define the data source for the DTC transfer as the ADC result register */


/* Reserve an area for the DTC vector table */
#pragma address dtc_vector_table = 0x00003000u

/* Declaration of the DTC vector table */
uint32_t dtc_vector_table[256u];
/* Reserve 16 bytes for the ADC trigger transfer data area */
uint32_t gDTC_S12AD_Transfer_Data[3u];
/* Variable to store ADC result transfered using DTC */
uint16_t usStore[256u];
/* Declare number of transfers container variable */
const uint8_t gNum_Transfers = 0x01u;
/* Declare a pointer to the DTC vector table */
uint32_t * gpVector_Table_Pointer = dtc_vector_table;



void InitDTC_FlashBGO(void)
    /* Clear the contents of the 'gDTC_Destination' array */
    if(memset(usStore, 0u, sizeof(usStore)) == NULL)
        /* Halt in while loop when errors detected */
    /* Protection off */
    SYSTEM.PRCR.WORD = 0xA503u;
    /* Cancel the DTC module clock stop mode */
    MSTP_DTC = 0u;
    /* Protection on */
    SYSTEM.PRCR.WORD = 0xA500u;       
    /* Ensure DTC is disabled */
    /* Reset the transfer skip flag */
    /* Use short address mode */
    /* Set the base address for calculating the DTC vector table address */
    DTC.DTCVBR = (uint32_t*)dtc_vector_table;


    /* Write to the MRA and SAR registers:
      - Source address is fixed
      - 16-bit word transfer
      - Select Normal transfer mode
    gDTC_S12AD_Transfer_Data[0] = ((uint32_t)0x10 << 24u) | ((uint32_t)DTC_SOURCE);
    /* Write to the MRB and DAR registers
      - Destination address is incremented after each data transfer
      - Transfer destination is the repeat area
      - An interrupt request to the CPU is generated when specified data transfer is completed
      - Chain transfers are disabled
    gDTC_S12AD_Transfer_Data[1] = ((uint32_t)0x08 << 24u) | ((uint32_t)usStore);
    /* Write to the CRA registers */
    gDTC_S12AD_Transfer_Data[2] = ((uint32_t)gNum_Transfers << 16u);


    /* Point to the S12AD vector in the DTC vector table
       VECT_S12AD_S12ADI0 = ADC scan end Vector 102
    gpVector_Table_Pointer += VECT_S12AD_S12ADI0;
    /* Store the data start address */
    *gpVector_Table_Pointer = (uint32_t)gDTC_S12AD_Transfer_Data;


    /* Enable DTC trigger on ADC conversion end */
    DTCE(S12AD,S12ADI0) = 1u;
    /* Set the transfer skip flag */



void InitADC_FlashBGO(void)
    /* Use the AN000 (Potentiometer) pin as an I/O for peripheral functions */
    PORT4.PMR.BYTE = 0x01u;
    /* Protection off */
    SYSTEM.PRCR.WORD = 0xA503u;
    /* Cancel the S12AD module clock stop mode */
    MSTP_S12AD = 0u;
    /* Protection on */
    SYSTEM.PRCR.WORD = 0xA500u;       
    /* ADC clock = PCLK/8
       Continuous scan mode
       Enable scan end interrupts */
    S12AD.ADCSR.BYTE = 0x50u;   
    /* Enable automatic clearing of ADDR0 register after it's been read */
    S12AD.ADCER.BIT.ACE = 0x1u;
    /* Selects AN000 */
    S12AD.ADANS0.WORD = 0x0001u;
    /* Set S12AD interrupt level to 7 */
    IPR(S12AD, S12ADI0) = 0x7u;
    /* Enable S12AD interrupt requests */
    IEN(S12AD, S12ADI0) = 0x1u;

    /* Start ADC conversions */
    S12AD.ADCSR.BIT.ADST = 1u;


/* The following interrup doesn't fire.... */

void Excep_S12AD0_S12ADI0(void)


      /*Set LED of evaluation board*/



Could anyone help me about the configuration of the DTC...







  • A few years ago I did some work on the DTC, Here are my notes from that time. Maybe this could help.
    There is no DTC interrupt
    Signal to DTC comes in on interrupt source’s vector (i.e. SCI1, TMR2)
    DTC transfer starts if
    - ICU: DTC Activation Enable Registers DTCERn = 1 (n=interrupt#)
    - When set, interrupt routed to DTC and not CPUWriting 0 to the IR flag prohibited(!?)
    - DTCE bit cleared after last data or block transferred
    o Interrupts again go to CPU = to the ISR(Normal & block mode)
    o Must set DTCE again
    Not all sources can trigger DTC - See ICU table
    But if DISEL bit (=DMA!) is set in CRB,interrupts go to CPU (ISR) after each transf
  • In reply to Carl S Stenquist:

    Thanks for your support Carl.
    I have spent a week for seraching the right configuration without success.
    I'm modifing the project to use DMA. It has a dedicated interrupt.
    It is a common application to sample a series of temperature values with ADC (DTC Normal transfer)
    and at the end(ADC interrupt), to take the medium value for example...
    It's very difficult to understand how to configure the DTC with the pheriperals interrupt on RX.
    I haven't found nothing about it in the forum.
    I hope in the future Renesas post an example or a few rows of code.
  • In reply to develop_h:

    Stupid question. have you checked interrupts are enabled in I flag of processor status word?
    You could consider to use PDG to configure RX63N peripherals.
  • In reply to FrankL:

    Sorry for my question. I was in panic last week.
    I have to submit my project to my boss.
    I'm new with RX Platform. I have resolved with DMA.
    Many thanks for the support.
  • This thread will be archived due to inactivity

    Mike Clements
    RenesasRulz Moderator