RH850 F1M R7F701548 Clock Controller Issue

Hi Guys,

Hope everyone is doing good.

I am currently facing an issue regrading clock configuration on RH850/F1M-R7F701548 MCU. I am using main oscillator of 8Mhz and PLL0/PPL1 are configured to have 80MHz output for CPLLCLK and PPLLCLK respectively.
Domain clock for CKSCLK_ATAUJ has been set to "PPLLCLK2".

Now the problem I am facing is

1. TAUJ0 should run at 40MHz as its source clock is PPLLCLK2. But its running on 80MHz.
2. CPUCLK2 is selected by as clock source for TAUJ1 by default but TAUJ1's counter is too slow which causes much delay in timer interrupt.

I have attached clock initialization source code.
Can anyone please check it? 

#include "dr7f701548_0.h"
/*============================================================================ */
/* Defines */
/*============================================================================ */
 /* Writing protected registers */
#define protected_write(preg,pstatus,reg,value)   \
do\
{\
(preg)=0xa5U;\
(reg)=(value);\
(reg)=~(value);\
(reg)=(value);\
} while((pstatus)==1u)
void BoardInit(void)
{
CLOCKS_init();
}
void CLOCKS_init(void)
 /* Prepare 8MHz MainOsz */
  if((MOSCS&0x04u) != 0x4u)                  /*check if MainOsc needs to be started */
  {
    MOSCC=0x03u;                            /* Set MainOSC gain (=8MHz) */
    MOSCST=0x8000u;                         /* Set MainOSC stabilization time to 4 ms */
    protected_write(PROTCMD0,PROTS0,MOSCE,0x01u);  /* Trigger Enable (protected write) */
    while (0x4u != (MOSCS&0x04u)){}           /* Wait for active MainOSC */
  }
  if((PLL0S&0x04u) != 0x04u)                  /*check if PLL0 needs to be started */
  {
    /* Prepare PLL*/
    PLL0C=0x00000227u;                       /*8 MHz MainOSC -> 80MHz PLL  */
    PLL0ST = 0x800u;                        /* Set MainOSC stabilization time */
    protected_write(PROTCMD1,PROTS1,PLL0E,0x01u);   /*enable PLL0 */
    while((PLL0S&0x04u) != 0x04u){}            /*Wait for active PLL0 */
  }
  
  if((PLL1S&0x04u) != 0x04u)                  /*check if PLL1 needs to be started */
  {
    /* Prepare PLL*/
    PLL1C=0x00000227u;                       /*8 MHz MainOSC -> 80MHz PLL  */
    protected_write(PROTCMD1,PROTS1,PLL1E,0x01u);   /*enable PLL1 */
    while((PLL1S&0x04u) != 0x04u){}            /*Wait for active PLL1 */
  }
  /* Set CPU Clock devider to 1 */
  protected_write(PROTCMD1,PROTS1,CKSC_CPUCLKD_CTL,0x01u);
  while(0x01u != CKSC_CPUCLKD_ACT){}
  /* Set CPU Clock to PLL (80MHz)*/
  protected_write(PROTCMD1,PROTS1,CKSC_CPUCLKS_CTL,0x03u);
  while(CKSC_CPUCLKS_ACT!=0x03u){}
  
  /* Source clock selection for C_AWO_TAUJ is PPCLLK2 i-e 40Mhz -> */
  protected_write(PROTCMD0,PROTS0,CKSC_ATAUJS_CTL,0x4U);
  while(0x4U != CKSC_ATAUJS_ACT){}
}