Hope everyone is doing good.
I am currently facing an issue regrading clock configuration on RH850/F1M-R7F701548 MCU. I am using main oscillator of 8Mhz and PLL0/PPL1 are configured to have 80MHz output for CPLLCLK and PPLLCLK respectively. Domain clock for CKSCLK_ATAUJ has been set to "PPLLCLK2".
Now the problem I am facing is
1. TAUJ0 should run at 40MHz as its source clock is PPLLCLK2. But its running on 80MHz. 2. CPUCLK2 is selected by as clock source for TAUJ1 by default but TAUJ1's counter is too slow which causes much delay in timer interrupt.
I have attached clock initialization source code. Can anyone please check it?
Have you resolved your issue?