SuperH (SH3) memory map/addr space question

I'm trying to wrap my head around the 29 bit addr bus on the SH3.  If I'm understanding correctly, this means at most 512M of memory can be addressed without using the MMU.

Also, since the top 3 bits are not utilized, what's the point of referencing one area over another?  These different memory areas (the P1 - P4 in the HW manual) should map to the same physical region, correct?  I do understand there are some system on chip registers (i.e. CCR2 at 0xA40000B0) in certain memory areas which would utilize the differences.

But a simple example like the reset vector default of 0xA0000000, what's the difference between that and 0x80000000? 

Other than the Renesas documentation, are there any books/reading material that I might find which can educate me a little bit in this area?