RZ/T1 - Clearing out pending data from the usb fifo's

I have a need to flush all pending data from the RZ/T1 usb fifo's (all data is not taken by the host, so need to reset).  Does anyone have suggestions or can point to example code?

  • Hi Jay,

    Were you able to figure out how to clear the pending data?

    RenesasRulz Forum Moderator


  • In reply to JB:

    hello sir
    i am working on rz/a1h microprocessor i want to turn on/off led of any port using GPIO pins using timers ,i have configured gpio pins but not able to set the timer plz can anyone of you share some sample codes or plz give me some suggestions

  • In reply to JB:

    Hi JB,
    I have not had success trying to clear out the USB Fifo's. Do you have any suggestions or example code?
  • In reply to Jay:


    I can only offer a clue (I have not used this):

    In the pipe control registers there is a bit called ACLRM (Auto Buffer clear Mode).

    For each Pipe you can set the sequence repeatedly between 1 and 0 until the buffer is cleared.

    Also in the (C,D0,D1)FIFOCTR registers there is also the BCLR bit that can be used to clear the CPU Buffer memory on the CPU side.

    You can find several notes in the USB section of the manual regarding this (search for ACLRM)

  • In reply to Martin:

    Thank you Martin for your reply. I have seen the BCLR bit and have tried to clear the D0 without success. Do you know where I should look to find out the status of the Fifo's? Is there a way to find out how many are full and how many are not? I'm very new to embedded, but have 25+ years on host side development, so some of my questions may be more of the "nubie" variety :) Thanks for any direction you can provide.
  • In reply to Jay:


    How is your project progressing?
    Have you been successfully able to flush your register?

    Mike Clements
    RenesasRulz Moderator
  • This thread will be archived due to inactivity.

    Mike Clements
    RenesasRulz Moderator