S7G2 writing to internal data flash during power off

I am just curious to know if there is a way on S7G2 to detect Power OFF condition to write couple of variables to internal data flash, and if there is a way to do that, the next question is would it have enough time to write 8 bytes before quitting.

If there is way then I don't have to worry about designing a super cap board/Circuitry that can hold the charge for 3-5 secs on power OFF.

I have a requirement to keep track some variables every 0.1 changes, and I don't want to write to memory every 0.1 change as I would hit the upper limit of 100,000 erase/write cycles in a couple of months.

Any input on this is much appreciated.

 

Thanks,

Sam

Parents
  • You could use external FRAM for close to unlimited write cycles, then you can make the write intervals so small that you may end up without any low voltage detection needed. Some FRAMs have a write protction pin, or internal LV-detection, or you could use one with 2 or more internal banks. With those functions you can protect the contents from beeing corrupted due to writes during falling supply.
    Another approach, in case you have a higher supply voltage from which the 3.3V processor supply is generated: In that case a drop in the, say 5V, can be the used to trigger an interrupt before the 3.3V start to drop. The time left is then only dependend from the bulk capacitor on the 5V. This can be optimized by the use of an DCC for the 3.3V and further by using a switch through or even boost-capable DCC, so you propably wont need a large cap.
    A further enhancement can be made in making all additional current consuming circuits -like interface chips- power-switchable via I/O-Pins.
    When the low-supply interrupt fires, all of this 'soon to be without power anyway' stuff is immediately switched off, leaving more or less only the processor on the supply to do some housekeeping. Of course it can be used to switch off unneccessary processor-internal peripherals as well to further save remainig time.
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  • You could use external FRAM for close to unlimited write cycles, then you can make the write intervals so small that you may end up without any low voltage detection needed. Some FRAMs have a write protction pin, or internal LV-detection, or you could use one with 2 or more internal banks. With those functions you can protect the contents from beeing corrupted due to writes during falling supply.
    Another approach, in case you have a higher supply voltage from which the 3.3V processor supply is generated: In that case a drop in the, say 5V, can be the used to trigger an interrupt before the 3.3V start to drop. The time left is then only dependend from the bulk capacitor on the 5V. This can be optimized by the use of an DCC for the 3.3V and further by using a switch through or even boost-capable DCC, so you propably wont need a large cap.
    A further enhancement can be made in making all additional current consuming circuits -like interface chips- power-switchable via I/O-Pins.
    When the low-supply interrupt fires, all of this 'soon to be without power anyway' stuff is immediately switched off, leaving more or less only the processor on the supply to do some housekeeping. Of course it can be used to switch off unneccessary processor-internal peripherals as well to further save remainig time.
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