I require a number of high priority ISR ,which do not interact with the main application threads, that cannot be delayed by the RTOS.
Please can you clarify how the SSP / ThreadX can be configured to achieve this on an S7?
Can nested interrupts be supported?
What is the relevance of the text in the SSP dropdown for setting interrupt priorities eg '(CM4:valid, CM0+:lowest-not valid if using ThreadX)?
In reply to Renesas Karol:
In reply to dburch:
All of your statements are correct. The number of priorities in Cortex-M cores is vendor-configurable ( https://community.arm.com/iot/embedded/b/embedded-blog/posts/cutting-through-the-confusion-with-arm-cortex-m-interrupt-priorities ) but on Synergy the relationship is as you described.
The bear minimum for an ISR implementation is following:
Although most peripherals will also require the interrupt flag to be cleared in their respective registers, before R_BSP_IrqStatusClear is invoked.