Making own ISR in S7G2

Here is an example on how to write a user defined ISR in SSP 1.x.x. For version 1.2.0 and later read replies further down in this post...

The example enables the GPT0 Capture Compare A Interrupt

I've used a similar process for additional ADC interrupts, so I think what is written below is correct!

BR, Richard

Enable the interrupt in the ICU tab of the Synergy Configurator.

Generate & Build the project.

If you were to run the project, as part of SystemInit (), there is a function call to bsp_irq_cfg ();

void SystemInit (void)

/* Initialize ELC events that will be used to trigger NVIC interrupts. */

bsp_irq_cfg();

This populates the Interrupt Enable Select Registers in the ICU.

This can be seen the IO Register ICU -> IELSR debug view

We now have to write the ISR.

In the source file, for example hal_entry.c, write the following:

To enable the interrupt, the interrupt has to be enable in the NVIC.

In source file, for example hal_entry.c, write the following:

In the ISR it will most likely to clear the interrupt flags that have been set in the IELSR and potentially, the peripheral.

In this example of the GPT, the code would be:

Here is an example on how to write a user defined ISR in SSP 1.x.x. For version 1.2.0 and later read replies further down in this post...

The example enables the GPT0 Capture Compare A Interrupt

I've used a similar process for additional ADC interrupts, so I think what is written below is correct!

BR, Richard

Enable the interrupt in the ICU tab of the Synergy Configurator.

Generate & Build the project.

If you were to run the project, as part of SystemInit (), there is a function call to bsp_irq_cfg ();

void SystemInit (void)

/* Initialize ELC events that will be used to trigger NVIC interrupts. */

bsp_irq_cfg();

This populates the Interrupt Enable Select Registers in the ICU.

This can be seen the IO Register ICU -> IELSR debug view

We now have to write the ISR.

In the source file, for example hal_entry.c, write the following:

To enable the interrupt, the interrupt has to be enable in the NVIC.

In source file, for example hal_entry.c, write the following:

In the ISR it will most likely to clear the interrupt flags that have been set in the IELSR and potentially, the peripheral.

In this example of the GPT, the code would be:

Thanks alot Richard Warner i will try and let you know if having some problems

Hello Bill,

As adboc mentioned, in SSP 1.2.0 vectors are inserted into the vector table by driver instances, rather than using pre-defined vector table rigged with ifdef's. Interrupts are enabled by "open" function of the driver, using the info from FMI.

Here are two steps required to specify your own ISR for peripheral signal (I'm using JPEG JDTI interrupt):

To add definition to the vector table and link the interrupt with your ISR function:

SSP_VECTOR_DEFINE(jpeg_jdti_isr, JPEG, JDTI);

peripherals with multiple channels (GPT) or units (ADC) should use one of the following:

SSP_VECTOR_DEFINE_CHAN(isr,ip,signal,channel);
SSP_VECTOR_DEFINE_UNIT(isr,ip,unit_name,signal,channel);

To enable the interrupt (set priority to 8):

ssp_feature_t ssp_feature = {{(ssp_ip_t) 0}};
ssp_feature.channel = 0;
ssp_feature.unit = 0U;
ssp_feature.id = SSP_IP_JPEG;

fmi_event_info_t event_info = {(IRQn_Type) 0U};
g_fmi_on_fmi.eventInfoGet(&ssp_feature, SSP_SIGNAL_JPEG_JDTI, &event_info);
NVIC_SetPriority(event_info.irq, 8);

R_BSP_IrqStatusClear(event_info.irq);
NVIC_ClearPendingIRQ(event_info.irq);
NVIC_EnableIRQ(event_info.irq);

(you may also have to enable the interrupt in the registers for that peripheral)

And to disable it (i.e. closing the driver) you should do the same, but omit call to NVIC_SetPriority and replace NVIC_EnableIRQ with NVIC_DisableIRQ.

Inside the ISR function, use R_BSP_IrqStatusClear(R_SSP_CurrentIrqGet()); to clear the flag in the ICU (you may have to clear one in the peripheral also).

Regards

UserDefineISR.zip

Here is an example written for the SK-S7G2 for E2 studio

It uses 3 GPT timers : 0,1 & 2.   

The example shows how to create a compare match interrupt for GPT0A, GPT1B and GPT2C

GPT0A isr turns on LED1, GPT1B isr turns on LED2 & GPT2C turns on LED3.

The GPT0 ISR that is set via the Synergy Configuration tool turns off the LEDs

Hopefully the comments in the code, in addition to the previous posts on this thread, will get you going

BR, Richard

Hello Richard!

Could you please give me a info where to find the label for a specific NVIC. Currently I'm trying to write my own ISR for a GPT on a S124 and I'm looking for a definition table for the interrupt sources.

Following functions need the right names, and I don't have them:

// Sets interrupt priority and initializes vector info

NVIC_SetPriority(*p_irq, ipl);

//Clear the ISR status

R_BSP_IrqStatusClear(event_info.irq);

//Clear pending ISR

NVIC_ClearPendingIRQ(event_info.irq);

//Interrupt has to be enable in the NVIC.

NVIC_EnableIRQ(...);

Do you know where to find them?

Regards,

Gregor

S7G2_SK_Blinky.zip

Not too sure what the issue is that you are having.

Please have a look at the attached project.  This is built for an S7G2_SK, using SSP 1.5.3. 

The 2 IRQ instances are added to HAL/Common.

They are opened in the Blinky Thread Entry.

The project also has a Display / GUIX thread for completeness.

Regards,

Richard