About S7G2 parallel data capture interface question

Hi Al, i am using S7G2 DK platform. use parallel data capture interface to capture one sensor data.
i define one vertical line and horizontal is 4095 byte.
but i use E2 debug this array, i see valid data are 4064 byte, 31 byte are invalid.

code declaration as below:
#if PDC_ON_PDC_BUFFER_USED_g_pdc
uint8_t g_pdc_frame_buffer[1][4095 * 1 * 1] BSP_ALIGN_VARIABLE_V2(64) BSP_PLACE_IN_SECTION_V2(".sdram");
#endif
pdc_instance_ctrl_t g_pdc_ctrl;
pdc_cfg_t g_pdc_cfg =
{ .bytes_per_pixel = 1,
.clock_division = PDC_CLOCK_DIVISION_2,
.endian = PDC_ENDIAN_LITTLE,
.hsync_polarity = PDC_HSYNC_POLARITY_HIGH,
.vsync_polarity = PDC_VSYNC_POLARITY_HIGH,
.p_buffer = (uint8_t *) g_pdc_frame_buffer,
.p_callback = g_pdc_user_callback,
.p_context = NULL,
.p_extend = NULL,
.p_lower_lvl_transfer = &g_transfer3,
.x_capture_pixels = 4095,
.y_capture_pixels = 1,
.x_capture_start_pixel = 0,
.y_capture_start_pixel = 0,
.frame_end_ipl = (3),
.irq_ipl = (3), };

How can i solution this problem?

 

BR,

 

Darren

  • Hello Darren!

    How's it going so far? I hope you could wait for our experts to respond to your inquiry.

    Thank you for waiting. All the best!

    Best Regards,
    Sai
    RenesasRulz Forum Moderator

    https://renesasrulz.com/
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  • In reply to Sai:

    Hello Sai

    I found pdc setting source code in r_pdc.c
    ssp_err_t R_PDC_CaptureStart (pdc_ctrl_t * const p_api_ctrl, uint8_t * const p_buffer)
    {
    ........
    num_blocks = (uint32_t) p_ctrl->x_capture_pixels; <--- 4095
    num_blocks *= p_ctrl->bytes_per_pixel; <---- 1
    num_blocks *= p_ctrl->y_capture_pixels; <--- 1
    num_blocks /= PDC_TRANSFER_SIZE;
    num_blocks /= PDC_TRANSFERS_PER_BLOCK;
    p_ctrl->p_lower_lvl_transfer->p_cfg->p_info->num_blocks = (uint16_t) num_blocks; < --- (4095 * 1 * 1)/4/8 = 127
    127 *32 = 4064 .
    4095 - 4064 = 31 byte
    this should cause data loss 31 byte.

    i use E2 Synergy License file is ssp_development_and_production.

    when i modified r_pdc.c and compile it. it will overwrite to original file.

    how can i get synergy license for modification these files?

    BR,

    Darren
  • In reply to darrencmf:

    With a Synergy project, files that are stored under a folder with Synergy in the name (synergy, synergy_cfg and synergy_gen), 

    are overwritten. The folders synergy_cfg and synergy_gen (and their sub-folders) contain files generated from the configuration of  the project. The folder Synergy (and it's sub-folders) contain source files that are extracted from the SSP packs.

     

     

    The issue is caused because the PDC triggers the transfer (by the DTC or DMAC) for every 32 bytes stored in the FIFO:-