I have a large array in SDRAM. I have found that I can read the data back correctly up to address 0x90400400. After that point, it begins to read incorrectly - it looks like it's either reading the value offset by 1KB, or perhaps always reading from the 0x904000xx location.
I am observing this on my SyG S7G2 modular dev kit and on our own hardware with the S7G2. In s7g2.ld we have SDRAM mapped to 0x90000000 with length 0x2000000.
I have seen the SDRAM timing configuration is incorrect on the S7G2-DK board. This note in the HW manual is not observed :-
a setting of RAS = 5 RCD = 2 and CL = 2 is used in the S7G2-DK board BSP (The BSP for the PE-HMI has RAS = 6 RCD = 3 and CL = 3 so meets the above requirement)
If I changed the CL or RCD setting to 3 so the above condition in the HW is met, then the test runs as expected in the attached project for the S7G2-DK :-
In reply to Jeremy: