QSPI flash support -custom S5D9


We are running into an error when trying to call  api ->pageprogram NOR flash device MT25Q512 with Custom S5D9,it always errors as SSP_ERR_UNSUPPORTED,I am not getting which mode is not supported .How do I add supported mode.

I run this hal application project of (s7Gk )  https://www.renesas.com/eu/en/software/D6001438.html on S5D9-PK kit,which is using windbond W25Q64FV,So its different from MT25Q512 since windboand nor flash is obsolete.We are using MT25Q.I am able to run this project on s5d9-PK successfully,it writes and read back too, 

Can suggest what can be the cause to SSP_ERR_UNSUPPORTED error .

I have observerd below,

1.SFMSDC register initialize value that is (0x000020c4)remains same after page write and read api executed in Example project,while in my project case,qspi.zip

this register initial value is  (0x000020c4) and when call to pageprogram api, SFMSDC register values changes to (0x0000ff04) 


2.Supply to IC is Ok.

 Please Assist me to correct the pageprogram error . 

  • SSP_ERR_UNSUPPORTED is used by the QSPI driver in the following places :-

    If the Open() API executed correctly, then SSP_ERR_UNSUPPORTED would be returned becuase of the 3 cases below :-

    The value of SFMSDC SFMXD bits is altered in the function bsp_qspi_xip_mode() in S5D9-PK bsp_qspi.c function to change the QSPI XIP mode :-


    where the values used are :-

    /* XIP entry and exit confirmation codes for the flash device */
    #define BSP_PRV_QSPI_W25Q64FV_XIP_ENTRY_CODE 0x20U // was 0
    #define BSP_PRV_QSPI_W25Q64FV_XIP_EXIT_CODE  0xffU

  • Thanks Jeremy for quick response .

    I confirmed ,open() api returns successfully ,now I understand unsupported error is due to invalid address range .

    extrenal flash  device I am using is of 512Mb(64 MB) so 3 byte addressing is fine.I have configure device in 3 byte addressing mode.

    Does it mean that I have to modify address range in e2 studio (Please show an option in e2 studio where to change the address range)

    I have set the device physical address as 0x60000000.

    Please correct me if misunderstood above.

    Is it possible for you to check what Configuration steps i have done in the code below


  • 3 byte addressing will only allow you to address 16MB of the QSPI device.

  • yes,Thanks

    It should write to address upto 16MB of device ,but its even giving me error for fix address too ..
     #define QSPI_DEVICE_ADDRESS 0x60000000
     #define BUFFER_LENGTH 2 
    uint8_t writeBuffer[BUFFER_LENGTH];

    err = g_qspi0.p_api->pageProgram(g_qspi0.p_ctrl, (uint8_t *) QSPI_DEVICE_ADDRESS, writeBuffer, BUFFER_LENGTH);

    I am accessing only first three address of qspi.but no luck..

    Can you please see (bsp_qspi.c and bsp_qspi.h) files in the project file shared above ,assist me to get it working.

  • Your project is for a custom board, I don't have the BSP for your custom board.
  • Is it possible for you to read over  BSP file created by me so that I can be confirm that BSP is correct,At this point I am really confused what to try to fix pageprogram() error.

    I made changes in bsp for 4-BYte addressing and qspi register,yet shows 3-byte register adrs mode.SFMSAC.SFMAS = 2,Also it never executes hal_entry file.


  • The MT25QL QSPI device is very similar to the N25Q QSPI device used on the V3.x S7G2-DK boards. I have taken the qspi BSP code from the DK board (I have stripped out the code for the Macronix QSPI device that is used on the V4.x S7G2-DK board, and fixed an issue where the non-volatile confg register is accessed with the incorrect byte order http://renesasrulz.com/synergy/f/synergy---forum/15195/ssp-qspi-driver-for-mt25ql256aba1ew7-on-s5d9/48242#48242 )

    I cannot test this on a MT25QL512 QSPI device however.



  • Hi,

    Thanks..I made changes as shared by you to read nonvolatile register with LSB first read and set 4-byte addressing modse,I can see SFMSAC updated correctly(SFMAS= 11 ,SFM4BC = 1)

    /* Read the non-volatile configuration of the device */

    uint32_t regval

    regval = R_QSPI->SFMCOM_b.SFMD ;                                                  /* Read the nv configuration register */
    regval |= (uint32_t)(R_QSPI->SFMCOM_b.SFMD << 8);                       /* Read the nv configuration register */
    R_QSPI->SFMCMD_b.DCOM = 1U;                                                       /* Close the SPI bus cycle */
    MT25Q_nv_cfg.status = regval;


    It  still throws SSP_UNSUPORTED for both pageprogram() and read() operation .

    so digged into QSP ssp (r_qspi.c)

    I think this error is due to

     1.qspi_program_param_check(p_ctrl, p_device_address, byte_count)

     2.qspi_validate_address_range( p_ctrl, p_device_address, byte_count)

     I cant check whats going inside r_qspi.c ,what is the significance of above two and is possible to see value of p_device_address,byte count.

    tried adding "p_device_address" in expression window but got errors from debugger.

    I have set device physical address as 0x6000000.(as per user manual).Please correct this if wrong




  • Hi Jeremy,

    I checked nonvolatile register and volatile register bit by bit.All seems ok to me.(As per default values stated in datasheet) I can see default values when bsp code is run first time.

    when I run the project , page program() api still errors SSP_UNSUPPORTED

    I have checked into r_qspi.c but can not  see whats actually happening inside param_check() and validate_address_range() to know what is causing it to throw SSP_UNSUPPORTED.

    I have checked that  DTR bit is disabled and XIP bit enabled.Bit 5 of nonvolatile register of n25q is "dont care" ,but bit 5 of MT25Q is "DTR".I have changed the bsp accordingly ,yet error exist.

    Can Renesas help to trace this error ? 

  • Are you using the files I posted?
  • Yes,I have  modified just 2 bits as per datasheet

    /** non-volatile configuration register for the Micron N25Q256A quad SPI flash device */

    typedef struct st_n25q256a_nv_cfg

    {   /*LDRA_INSPECTED 381 S Anonymous structures and unions are allowed in SSP code. */



           uint16_t    entire_cfg;

           /*LDRA_INSPECTED 381 S Anonymous structures and unions are allowed in SSP code. */



           uint16_t  address_bytes              : 1; ///< Defines the number of address bytes for a command. 0 = enable 4 byte

                                                     // address, 1 = enable 3 byte address (default)

           uint16_t  segment_select_128mb       : 1; ///< Selects a 128Mb segment as default for 3B address operations.  0 =

                                                     // Upper 128Mb segment, 1 = Lower 128Mb segment (Default)

           uint16_t  dual_io_protocol           : 1; ///< Enables or disables dual I/O protocol. 0 = Enabled, 1 = Disabled

                                                     // (Default, Extended SPI protocol)

           uint16_t  quad_io_protocol           : 1; ///< Enables or disables quad I/O protocol. 0 = Enabled, 1 = Disabled

                                                     // (Default, Extended SPI protcocol)

           uint16_t  reset_hold                 : 1; ///< Enables or disables hold or reset. 0 = Disabled, 1 = Enabled

                                                     // (Default)

           uint16_t  dtr_protocol               : 1; ///< Double transfer rate

           uint16_t  output_driver_strength     : 3; ///< Optimizes impedance at VCC/2 output voltage.

           uint16_t  xip_mode_at_power_on_reset : 3; ///< Enables the device to operate in the selected XIP mode immediately

                                                     // after power-on reset.

           uint16_t  number_dummy_clock_cycles  : 4; ///< Sets the number of dummy clock cycles subsequent to all FAST READ

                                                     // commands. The default setting targets the maximum allowed frequency and

                                                     // guarantees backward compatibility.



    } n25q256a_nv_cfg;

    typedef struct st_n25q256a_flag_status


       /*LDRA_INSPECTED 381 S Anonymous structures and unions are allowed in SSP code. */



           uint32_t    entire_cfg;

           /*LDRA_INSPECTED 381 S Anonymous structures and unions are allowed in SSP code. */



           uint8_t  addressing_4_byte_mode : 1;      ///< 0 = 3 bytes addressing, 1 = 4 bytes addressing

                                                     // 0 = Ready, 1 = Busy

           uint8_t  protection             : 1;      ///< Indicates whether a PROGRAM operation has attempted to modify the

                                                     // protected array sector or access the locked OTP space. 0 = Clear, 1 =

                                                     // Failure or protection error

           uint8_t  program_suspend             : 1; ///< Indicates whether a PROGRAM operation has been or is going to be

                                                     // suspended. 0 = Not in effect, 1 = In effect

           uint8_t                              : 1; ///  0 =  (Default)    unused

           uint8_t  program                     : 1; ///< An attempt to program a 0 to a 1 when VPP = VPPH and the data pattern

                                                     // is a multiple of 64 bits. 0 = Clear, 1 = Failure or protection error

           uint8_t  erase                       : 1; ///< Indicates whether an ERASE operation has succeeded or failed. 0 =

                                                     // Clear, 1 = Failure or protection error

           uint8_t  erase_suspend               : 1; ///< Indicates whether an ERASE operation has been or is going to be

                                                     // suspended. 0 = Not in effect, 1 = In effect

           uint8_t  program_or_erase_controller : 1; ///< Indicates whether a PROGRAM, ERASE, WRITE STATUS REGISTER, or WRITE

                                                     // NONVOLATILE CONFIGURATION command cycle is in progress. 0 = Busy, 1 =    // Ready                                          



    } n25q256a_flag_status;

  • Do you have 3 or 4 byte addressing enabled? What the address you are trying to program in the QSPI device?
  • I have enabled 4 byte addressing mode.
    HAL application project as a reference , trying to write as
    Pageprogram(device-physical address, writebuffer, bytecount)

    bytecount is 32
    Physical address :0x6000000
  • Physical address 0x6000000 is not in QSPI address space (0x60000000 to 0x63FFFFFF)
  • Could you share where is QSPI address space range is mentioned,
    When external flash device is interfaced, what can be the address space range.?