crosstalk in ADC Periodic framework

hello everyone,

     i'm working on synergy s7g2 using  synergy stater kit  for reading adc value using two channels with a high impedance source ( aproximately above 5 M ohms for each channels).

and i'm using adc peroidic framework because i experenice crosstalk in Hal adc driver , while search for the reason in synergy forum someone answer the same question by recommding to use adc peroidic framework , because it provides to crosstalk in mutichannels. Even though i'm using the adc peroidic framework for getting two adc values again  i'm experience same crosstalk problem, 

i reduced the ADCLK frequency to 7.5MHz hoping that it may increase the interval between the stopping conversion of one channel and starting conversion of one channel  between that two adc channels  may rectify the crosstalk problem  but the crosstalk problem contiues, and i reduced the bit resolution from 12 bit to 8 bit so the conversion of channel can be done quickly.

Is there anyway to reduce the crosstalk of two channels, 

my config setting are 

adc uint-0




internal calbration- disabled

sample and hold -disabled

add and average - disabled

Group A channel


plz help..

  • Have you modified the default ADC sampling state count using the ADC HAL driver (R_ADC_SetSampleStateCount) ?


  • In reply to Jeremy:

    hi Jeremy,
    Thanks for the reply, yes sir i have used p.api->sampleStateCountSet() which passes two arguments one is adc control and other one is passing a structure having selected channel and unsigned value from 0 to 255 to set the sample state count,

    my code will be like this

    first is create the struct

    adc_sample_state_t sple_ste ={

    then i used this struct in samplestateset api after opening the adc driver

    but i used this function when ADCLK is 60mhz not in 7.5Mhz. once again i try and post the result .

    once again thanks for your reply
  • Please look up the ADC input capacitance and calculate the settling time necessary for an operation with crosstalk rduced to your needs. With above 5M source impedance you possibly end up in the milliseconds range. And then there will be other problems that will always compromise your readings, so at first you will have to reduce your input impedadance by at least a factor of 100, better 1000.
  • In reply to josh222:

    thanks for the quick @reply josh222 ,
    I can't reduce the source impedance value because i have measure the resistance value which will variable between 1M ohms to 5Mohs or may be above so i can't reduce the source impedance , and i checked the datasheet i didn't got what is ADC sample and hold cicurit capcitance value .

    i have increased the sample and hold count to 255 in configurator and i set the ADCCLK value to 3.5Mhz now the crosstalk have reduce but not as for our requirement , i gone through some documents to calculate the value for the decoupling capcitor , some documents says the external decouple capcitor from the sensor should the greater than internal sample and hold capcitor value. I gone through the datasheet of s7g2 to know the value of internal capcitance but i find it.

    currently i didn't use any decoupling capacitor to the input of the ADC channel.

    i'm sorry to reply this late , got some personal things and i not a professional coder in ADC , so plz help me

    thanks a lot
  • In reply to yuva:

    You can reduce the impedance the ADC input sees, thats what OP-Amps are for.
    If I remember right, the ADCs have an input capacity about 30pf.
    It is given in the HW-Manual, and the maximum source impedance all the specs are valid for, too.

    A capacitor at the ADC-input pin would help to get rid of the cross talk, but it will reduce the response time of the whole setup. But there are some other problems the high impedance will introduce you can't get rid of with that cap. Leakage currents for example. In the end you need an OP-Amp if you want reproducable, stable, and fast readings.