i'm working on synergy s7g2 using synergy stater kit for reading adc value using two channels with a high impedance source ( aproximately above 5 M ohms for each channels).
and i'm using adc peroidic framework because i experenice crosstalk in Hal adc driver , while search for the reason in synergy forum someone answer the same question by recommding to use adc peroidic framework , because it provides to crosstalk in mutichannels. Even though i'm using the adc peroidic framework for getting two adc values again i'm experience same crosstalk problem,
i reduced the ADCLK frequency to 7.5MHz hoping that it may increase the interval between the stopping conversion of one channel and starting conversion of one channel between that two adc channels may rectify the crosstalk problem but the crosstalk problem contiues, and i reduced the bit resolution from 12 bit to 8 bit so the conversion of channel can be done quickly.
Is there anyway to reduce the crosstalk of two channels,
my config setting are
internal calbration- disabled
sample and hold -disabled
add and average - disabled
Group A channel
Have you modified the default ADC sampling state count using the ADC HAL driver (R_ADC_SetSampleStateCount) ?
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