RX Cascading MTU2 and MTU1 also MTU8 and MTU7

Found the problem......   MTU 1 uses TCNT overflows NOT TGRA resets of TCNT.!!!!!!

SO cascading of timers is really only meant to cascade them as counters.

Solution: Use the MTU 2 overflow to trigger an interrupt which you use to reload TCNT and allow it to overflow from there.

I am trying to use MTU 2 and 1 to drive a DMA transfer. If the source for MTU 1 is PCLK all works correctly. But when I use MTU 2 as the clock source for MTU 1. Doesn't work. Following are their setups:

void InitDMATimer2(void)
{
  /* Enable and Stop Timers */
  MSTP(MTU2) = 0;           // cancel stopped state
  MTUA.TSTR.BYTE &= 0x01;   // Stop timers 1,2,3,4

  /* MTU2 - DMA Counter */
  MTU2.TCR.BIT.CCLR = 1;    // TCNT clears on TGRA match
  MTU2.TCR.BIT.TPSC = 7;    // PCLK / 64 == 750 KHz
  MTU2.TCR.BIT.CKEG = 0;    // Count on Rising Edge

  MTU2.TIOR.BYTE = 0;       // No IO

  MTU2.TSR.BIT.TCFD = 1;    // count up

  MTU2.TGRA = 15;           // set for 5 uSec (For Default Accel/Decel/VI/VM)

  MTU2.TCNT = 0;

//   MTU2.TIER.BIT.TGIEA = 1;  // enable interrupt

  MTUA.TSTR.BIT.CST2 = 0;   // start timer later

//   // Enable Timer interrupt
//   IPR(MTU2, TGIA2) = 8;
//   IEN(MTU2, TGIA2) = 1;
}

/*
 ** InitDMATimer1
 *
 *  FILENAME: D:\Position_Control\Renesas_Motion_With_Float\Asic.c
 *
 *  PARAMETERS: none
 *
 *  DESCRIPTION: Sets up Timer1 of (Least Significant) DMA Timers
 *
 *  RETURNS: nothing
 *
 *
**/
void InitDMATimer1(void)
{
  /* Enable and Stop Timers */
  MSTP(MTU1) = 0;           // cancel stopped state
  MTUA.TSTR.BYTE &= 0x01;   // Stop timers 1,2,3,4

  /* MTU1 - DMA Counter */
  MTU1.TCR.BIT.CCLR = 1;    // TCNT clears on TGRA match
  MTU1.TCR.BIT.TPSC = 7;    // Clock Source (Timer2 or PCLK)
  MTU1.TCR.BIT.CKEG = 0;    // Count on Rising Edge

  MTU1.TIOR.BYTE = 0;       // No IO

  MTU1.TSR.BIT.TCFD = 1;    // count up

  MTU1.TGRA = 299;          // set for 2.99 mSec (For Default Accel/Decel/VI/VM)

  MTU1.TCNT = 0;

  MTU1.TIER.BIT.TGIEA = 1;  // enable interrupt

  MTUA.TSTR.BIT.CST1 = 0;   // start timer later

  // Enable Timer interrupt
  IPR(MTU1, TGIA1) = 8;
  IEN(MTU1, TGIA1) = 1;

}

I used the interrupt settings in MTU 2 to verify for myself that it was running. It was.

The RX hardware manual shows a Cascade arrangement, but glosses over how to set them up.

I suspect the setup is missing something, but what is eluding me.

Thanks

  • I seem to remember that MTU2 had to overflow to increment MTU1, as you have it clearing on capture it never does.

    I needed a similar thing to count 'lost clocks' and ended up wiring two pins together (MTIO2CB to MTU1 MTCLKB input) in hardware to get what I wanted.

    God I love that hardware manual.....