RL78G12 FSL_Init for IAR

Hello

I used the RL78G12 R5F10279 MCU and it have some problem about FSL_Init function.
When i use this function, it always reture the 0x05.

I have read the datasheet, it say HOCO isn't start or parameter is error, but it's impossible.
My hardware didn't have X1 Osc and i checked the Buzzer output pin is 24MHz from the High speed On chip.

This is my code : 

RL78 High speed On chip Init :

0x000C2H = 0xE0;
PIOR = 0x00;
CKC = 0x00;
HOCODIV = 0x00;
IAWCTL = 0x00;

RL78 FSL init :

fsl_u08 my_fsl_status;
fsl_descriptor_t fsl_descr;

fsl_descr.fsl_flash_voltage_u08 = 0x00;
fsl_descr.fsl_frequency_u08 = 0x18;
fsl_descr.fsl_auto_status_check_u08 = 0x01;

my_fsl_status = FSL_Init((__far fsl_descriptor_t*)&fsl_descr);

Can anyone help me if my code have any problem?

Thanks

  • Your fsl_descriptor_t values look correct for 24MHZ system clock, High Speed mode, and FSL Status Check Internal mode.

    However, my experience is that having an error in the FSL_Init prototype declaration can cause the FSL_Init error of 0x05, even if the fsl_descriptor_t values are valid.

    Here are the correct FSL_Init prototypes listed on page 27 of RL78 FSL library User's manual, R01US0016ED0105.
    So please make sure you have the correct FSL_Init prototype declaration for the RL78 C-compiler you are using.

    C Language Interface (CA78K0R version)
    fsl_u08 FSL_Init(__far fsl_descriptor_t* descriptor_pstr)

    C Language Interface (IAR version)
    __far_func fsl_u08 FSL_Init(const __far fsl_descriptor_t __far*descriptor_pstr);

    C Language Interface (GNU version)
    fsl_u08 FSL_Init(__far fsl_descriptor_t __far *descriptor_pstr)__attribute__ ((section ("FSL_FCD")));

    C Language Interface (CC-RL version)
    fsl_u08 __far FSL_Init(const __far fsl_descriptor_t*descriptor_pstr);

    Regards,
    Mike
  • In reply to Mike Clodfelter:

    Hello Mike

    Thanks

    I tried the prototype declaration for CA78K0R, IAR and CC-RL, but the problem still exists.
  • In reply to LBJ:

    Hi LBJ,

    Sorry, but I didn't see you were using IAR EWRL78 the first time. Which version of EWRL78 are you using? v1.x (XLINK linker type) or v2.x/v3.x (ILINK Linker type)?
    Which FSL library are you using?

    Thanks,
    Mike
  • In reply to Mike Clodfelter:

    Hi Mike,

    Thanks again,

    I used the CCRL V3.0 it will return 0x05,
    CA78K0R will tell me it's not object,
    and the IAR V2.1 when i stepping to function FSL_Init, the E1 will be dead.
  • In reply to LBJ:

    Hi everyone,

    I have a similar problem too. I have an RL78 / G14 and I use the IAR V4.10.1 environment. When I start the debugging application I can not go beyond the function FSL_Init ().

    This is the source code:

    #define FULL_SPEED_MODE (0x00) /* Initial setting value ( full-speed mode ) */
    #define FREQUENCY_32M (0x20) /* Initial setting value ( frequency ) */
    #define INTERNAL_MODE (0x01) /* Initial setting value ( internal mode ) */

    fsl_descriptor_t InitArg;

    /* ---- Set argument of FSL_Init() ---- */
    InitArg.fsl_flash_voltage_u08 = FULL_SPEED_MODE;
    InitArg.fsl_frequency_u08 = FREQUENCY_32M;
    InitArg.fsl_auto_status_check_u08 = INTERNAL_MODE;

    ret = FSL_Init( &InitArg );


    The prototype for FSL_Init is
    extern __far_func fsl_u08 FSL_Init(const fsl_descriptor_t __far * descriptor_pstr);

    Any suggestions? Thanks.
  • In reply to LBJ:

    Hi everyone,

    I have a similar problem on RL78/G13 and I use the IAR V4.10.1 and FSL Lib V2.21 (for IAR V2)
    When I start the debugging application I can not go beyond the function FSL_Init ()

    How to fix this?
  • In reply to Ibrahim:

    Which RL78/G13 device number are you using?
    If the Code Flash size is 64KB or 256KB or 512KB, generally you will need to specify User RAM starting at 1KB above the start of RAM. Refer to the Self-RAM document at:
    www.renesas.com/.../r20ut2944ej0302_rl78.pdf

    Additional issues to look for:
    1. The fsl_descriptor must have correct values:
    a. if using FULL_Speed mode, the Option byte 000C2H must have HIGH SPEED Mode, and VDD must be 2.4V or greater for CPU *** speed = > 8MHZ to 16MHZ or VDD must be 2.7V or greater for CPU Clock Speed > 16MHZ.
    b. if using external clock on X1/X2 pins to run CPU, the external clock speed must be specified in fsl_frequency_u08. However, internal HOCO must still be enabled when running FSL. The fsl_frequency must be set to 0x01 to 0x14 max (for 1MHZ to 20MHZ) if using external clock for CPU, or 0x01 to 0x20 max if using internal HOCO clock.

    2. Please verify that you have all the FSL memory sections specified in your .icf linker file
    a. if using status check internal mode (SCI)
    FSL_FCD in ROM
    FSL_FECD in ROM
    FSL_BCD in ROM
    FSL_BECD in ROM
    FSL_RCD in ROM or RAM
    b. If using status check user mode (SCU)
  • In reply to Ibrahim:

    Which RL78/G13 device number are you using?
    If the Code Flash size is 64KB or 256KB or 512KB, generally you will need to specify User RAM starting at 1KB above the start of RAM. Refer to the Self-RAM document at:
    www.renesas.com/.../r20ut2944ej0302_rl78.pdf

    Additional issues to look for:
    1. The fsl_descriptor must have correct values:
    a. if using FULL_Speed mode, the Option byte 000C2H must have HIGH SPEED Mode, and VDD must be 2.4V or greater for CPU *** speed = > 8MHZ to 16MHZ or VDD must be 2.7V or greater for CPU Clock Speed > 16MHZ.
    b. if using external clock on X1/X2 pins to run CPU, the external clock speed must be specified in fsl_frequency_u08. However, internal HOCO must still be enabled when running FSL. The fsl_frequency must be set to 0x01 to 0x14 max (for 1MHZ to 20MHZ) if using external clock for CPU, or 0x01 to 0x20 max if using internal HOCO clock.

    2. Please verify that you have all the FSL memory sections specified in your .icf linker file
    a. if using status check internal mode (SCI)
    FSL_FCD in ROM
    FSL_FECD in ROM
    FSL_BCD in ROM
    FSL_BECD in ROM
    FSL_RCD in ROM or RAM
    b. If using status check user mode (SCU)
  • In reply to Mike Clodfelter:

    Hi Mike,

    Thanks for advice.
    I using R5F100LEA for EVK Board "RSKRL78G13-3".
    And my product using R5F100LGA , EAU 1M Unit.

    For your Information as below.
    - Compiler "IAR C/C++ Compiler V4.10.1.2197 for RL78"
    - Library " RL78 Self-Programming Library T01‚Äč V3.00 and IAR V2.21"
    - Internal clock 24.00 MHz., Config to SCI mode and Voltage 3.3V

    fsl_descriptor.fsl_flash_voltage_u08 = (fsl_u08)0; // Full Speed Mode Voltage > 2.9V
    fsl_descriptor.fsl_frequency_u08 = (fsl_u08)24; // Frequency 24 Mhz.
    fsl_descriptor.fsl_auto_status_check_u08 = (fsl_u08)1; // Auto Check Internal

    For Linker File:
    I only modify the address of RAM to support FSL 1Kbyte from the original of IAR linker file.

    define exported symbol __link_file_version_2 = 1;

    initialize by copy with simple ranges, packing = auto { rw, R_DATA, R_BSS, R_DATAF, R_BSSF, R_SDATA, R_SBSS };
    do not initialize { section *.noinit };

    define memory mem with size = 1M;

    // Set the symbol __RESERVE_OCD_ROM to 1 to reserve the OCD area for debugging.
    // IDE: Symbol can be defined within the project settings here:
    // "Project"-->"Options..."->"Linker"-->"Config"-->"Configuration file symbol definitions"
    // Symbol definition: __RESERVE_OCD_ROM=1
    // Command line: --config_def __RESERVE_OCD_ROM=1

    if (isdefinedsymbol(__RESERVE_OCD_ROM))
    {
    if (__RESERVE_OCD_ROM == 1)
    {
    reserve region "OCD ROM area" = mem:[from 0x0FE00 size 0x0200];
    }
    }

    define region ROM_near = mem:[from 0x000D8 to 0x0FFFF];
    define region ROM_far = mem:[from 0x000D8 to 0x0FFFF];
    define region ROM_huge = mem:[from 0x000D8 to 0x0FFFF];
    define region SADDR = mem:[from 0xFFE20 to 0xFFEDF];
    define region RAM_near = mem:[from 0xFF300 to 0xFFE1F];
    define region RAM_far = mem:[from 0xFF300 to 0xFFE1F];
    define region RAM_huge = mem:[from 0xFF300 to 0xFFE1F];
    define region VECTOR = mem:[from 0x00000 to 0x0007F];
    define region CALLT = mem:[from 0x00080 to 0x000BF];
    define region EEPROM = mem:[from 0xF1000 to 0xF1FFF];

    Note, The sample linker file from FSL V3.00 doesn't match the version of IAR 4.10. It has value below.

    define exported symbol __link_file_version_2 = 1;

    After That, See my code as below,

    /* initialize self-programming environment */
    fsl_status = 0x00;

    fsl_descriptor.fsl_flash_voltage_u08 = (fsl_u08)0; // Full Speed Mode Voltage > 2.9V
    fsl_descriptor.fsl_frequency_u08 = (fsl_u08)24; // Frequency 24 Mhz.
    fsl_descriptor.fsl_auto_status_check_u08 = (fsl_u08)1; // Auto Check Internal

    fsl_status = FSL_Init((__far fsl_descriptor_t*)&fsl_descriptor);

    if(fsl_status != FSL_OK)
    {
    ErrorHandler(FSL_INVERTBOOTFLAG);
    }

    delayTimeMs(1000);

    FSL_Open();
    FSL_PrepareFunctions();
    FSL_PrepareExtFunctions();

    pointer_version_str = FSL_GetVersionString();

    sprintf((char *)sString,"\r\nInit FSL Version:%s",pointer_version_str);
    uart0SendString(sString);
    delayTimeMs(100);

    For issues:(Test on EVK Board R5F100LEA)
    I using FSL_Erase(), FSL_BlankCheck(), FSL_Write() and other.
    So, Some time it can running, But some Time it jump to 0 address.

    for (i = 8; i < 64; i++)
    {
    fsl_status = FSL_Erase((fsl_u16)i);
    if (fsl_status != FSL_OK)
    {
    ErrorHandler(FSL_ERASE);
    }
    }

    I don't understand why ?
    I try to put the delay 1 Sec. But does not work.

    for (i = 8; i < 64; i++)
    {
    fsl_status = FSL_Erase((fsl_u16)i);
    if (fsl_status != FSL_OK)
    {
    ErrorHandler(FSL_ERASE);
    }
    delayTimeMs(1000);
    }

    Can do you help me?

  • In reply to Ibrahim:

    Maybe you are getting Repeating CPU Resets.

    Please check the value of RESF one time at beginning of main().

    If RESF is non-zero, please check which bit is source of CPU reset condition:

    WDTRF: Internal reset by watchdog timer program loop detection

    LVIRF: Internal reset by comparison of supply voltage of the voltage detector (LVD) and detection voltage

    TRAP: Internal reset by execution of illegal instructionNote

    RPERF: Internal reset by RAM parity error

    IAWRF: Internal reset by illegal-memory access

     

    Regards,

    Mike

  • In reply to Mike Clodfelter:

    Hi Mike,

    Thanks, I will try to check with your advice and tell you again.

    So, Right now I try to running code without debugger mode and E1 tool.
    The code can running and write/erase flash with FSL.

    I not understand why not work in debugger mode.

    I want to use debugger to see about some thing bug in my code.

    Thank you.