RL78/F13 Evaluation Board- External clock issue

We are trying to use External oscillator instead of Hosc(High speed on chip oscillator) in RL78/F13 evaluation board .

External oscillator in evaluation board is 4Mhz. We are trying to convert this in 24Mhz through PLL. In optionbyte we have set the frequency of 8Mhz, i.e.0xEA@00C2u.

Following is the code that we are using for setting External Frequency as clock-(generated from cs+)

Code-

volatile uint32_t w_count;
uint8_t temp_stab_set;
uint8_t temp_stab_wait;

/* Set fSL */
SELLOSC = 1U;
/* Set fMX */
CMC = _40_CGC_HISYS_OSC | _00_CGC_SUB_PORT | _00_CGC_SYSOSC_UNDER10M | _00_CGC_SUBMODE_DEFAULT;
OSTS = _07_CGC_OSCSTAB_SEL18;
MSTOP = 0U;
temp_stab_set = _FF_CGC_OSCSTAB_STA18;

do
{
temp_stab_wait = OSTC;
temp_stab_wait &= temp_stab_set;
}
while (temp_stab_wait != temp_stab_set);

/* Set fMAIN */
MCM0 = 1U;

while (MCS == 0U)
{
;
}

/* Set fPLL */
PLLCTL = _40_CGC_LOCKUP_WAIT_8 | _00_CGC_PLL_BELOW_32MHZ | _00_CGC_PLL_DIVISION_2 | _00_CGC_PLL_MULTIPLY_X12;

/* Change the waiting time according to the system */
for (w_count = 0U; w_count <= CGC_PLLWAITTIME; w_count++)
{
asm("nop");
}

PLLON = 1U;

while ((PLLSTS & 0x80U) == 0U)
{
;
}

MDIV = _00_CGC_FMP_DIV_DEFAULT;
/* Set fMP to PLL clock select mode */
SELPLL = 1U;

while ((PLLSTS & 0x88U) != 0x88U)
{
;
}

/* Set fSUB */
XTSTOP = 1U;
/* Set fCLK */
CSS = 0U;
/* Set fIH */
HIOSTOP = 0U;
/* Set RTC clock source */
RTCCL = _00_CGC_RTC_FMX | _42_CGC_RTC_DIV122;
/* Set Timer RD clock source to fCLK, fMP */
TRD_CKSEL = 0U;

 

After doing this,control is getting into main() first line. PLL is locked when we see register-view in main().

When we stepin and break, the control is getting hang and showing the following messages .

With Internal oscillator settings, code is working fine. 

Could you please tell us what is there that we are doing wrong.

  • Hello Aki,

    we have same issue with same configuration.
    We are not able to fix the discribed issue. Did you already found a solution for debugging problems with external oscillator?

    Best Regards,
    Steve

  • Your code says that value 0x40 (01000000 binary) is being written to PLLCTL register.
    However, the screenshot of PLLCTL register shows value 0x97 (10010111 binary). This is PLL x16 multiply and divide by 4. Is this the correct screenshot?

    Is it possible some other code is writing 0x97 value to PLLCTL?
    For PLLCTL = 0x97, fMAIN = 8MHZ is the only allowed input frequency per the RL78/F13 HW User's manual.

    -Mike

  • In reply to Steve:

    For us the problem sloved by using the correct settings at E1 Hardware Setup in IAR Workbench. Changed setting of main clock to a frequenz of 8Mhz solved the debug problem.