Writing to CSHI0 registers on RH850/P1HC

I am trying to write to CSHI0  registers CTL0,1 and 2 and CFG registers to configure CSHI0 spi communication after setting up the registers when i view the memory location in the multi debugger the values are not reflecting and i am not getting any output. While my port configuration registers values are reflected in the debugger. So, can you help me how to write to these registers to up my spi communication?

  • hello David thanks for the reply, now i am able to write to the csih registers.

    Also, i had one more doubt regarding the same.

    I have configured 2MHz baud rate and transmit only buffer mode and was expecting a clock on sck pin using analyzer but only getting high low from the pin. I don't know what is wrong with my configurations or i am missing any steps? and I am not sure my transmission is happening or not also, my receive interrupt is generated. But RX0W contains zeros so can you guide me?

    #pragma ghs interrupt
    void INTCSIH0TIR (void)
    sts_rx[rx_ind] = CSIH0RX0W;

    void CSIH0_Port_init(void){
    /*Configure CSIH0 port5
    *CSIH0CSS1 SPI_DSI3.SS1 P5_1 O
    *CSIH0CSS0 SPI_DSI3.SS0 P5_4 O
    PFCE5 &= 0xFF0DU; /* 1111111100001101*/
    PFC5 |= 0x00F2U; /* 0000000011110010*/
    PMC5 |= 0x00F2U; /* 0000000011110010*/
    PM5 |= 0x0080U; /* 0000000010000000*/
    PM5 &= 0xFF8DU; /* 1111111110001101*/
    PIPC5 |= 0x0060U; /* 0000000001100000*/

    MSR_LM10 = 0x00000000;

    void CSIH0_Mode_Config(void){

    /*Stop transmission*/
    CSIH0.CTL0.UINT8 = 0x00;

    /* CSIH0CTL1 =
    - //[31:19]: reserved
    - // (0x0 <<18) //[18]: CPU-controlled high-priority communication function
    - // disabled
    - (0x0 <<17) //[17]: default level of CSIHTSCK is low
    - |(0x0 <<16) //[16]: normal interrupt timing of INTCSIH0IC
    - |(0x0 <<8) //[15:8]: all chip select signals are active low
    - |(0x0 <<7) //[7]: extended data length mode enabled
    - |(0x0 <<6) //[6]: job mode enabled
    - |(0x0 <<5) //[5]: data consistency check disabled
    - |(0x1 <<4) //[4]: chip select signal returns to the inactive level
    - // after last transfer
    - |(0x0 <<3) //[3]: loop-back mode deactived
    - |(0x0 <<2) //[2]: no interrupt delay is generated
    - |(0x0 <<1) //[1]: handshake function disabled
    - |(0x0); //[0]: slave select input ignored*/

    CSIH0.CTL1 = 0x00000010UL;

    //CSIH0CTL2 = (0x0 <<13); //[15:13]: referenc clock (PRSOUT) is PCLK
    //[12:0]: reserved
    CSIH0.CTL2 = 0x0000U;

    CSIH0BRS0 = 20; // BRS0 clock = PRSOUT/(4 * CSIH0BRS0)

    CSIH0MCTL0 =
    //[15:10] reserved
    (0x2 <<8) //[9:8] transmit-only buffer mode selected
    //[7:5] reserved
    |(0x0); //[4:0] no time-out detection (in FIFO mode only)

    CSIH0MCTL1 =
    //[31:23] reserved
    (0x0 <<16) //[22:16] number of remaining transmit data for setting FIFO
    // empty flag and INTCSIH0IC generation (buffer empty)
    //[15:7] reserved
    |(0x0); //[6:0] number of remaining reception data space in FIFO
    // mode for INTCSIH0IR generation (buffer full)

    CSIH0CFG0 = // Configuration of CS0 signal
    (0x0 <<30) //[31:30] transfer clock is set according to CSIH0BRS0
    |(0x0 <<28) //[29:28] no parity transmission/expectation
    |(0x8 <<24) //[27:24] data length = 16 bits
    |(0x0 <<19) //[19] dominat setting of chip select signal
    |(0x0 <<18) //[18] MSB first transmission/reception
    |(0x1 <<17) //[17] clock phase selection
    |(0x0 <<16) //[16] data phase selection
    |(0x0 <<15) //[15] no idle state insertion between consecutive transfers
    |(0x0 <<12) //[14:12] idle time is 0.5 transmission clocks cycles
    |(0x0 <<8) //[11:8] hold time is 0.5 transmission clocks cycles
    |(0x0 <<4) //[7:4] inter-delay time is 0.0 transmission clocks cycles
    |(0x0); //[3:0] setup time is 0.5 transmission clocks cycles

    EIC88 = 0x004fU;

    CSIH0PWR = 1;


    void CSIH0_Write(void){

    unsigned long tempTxW = 0;
    unsigned long txdatabuf[4];
    CSIH0_NumOfData = 4;
    txdatabuf[0] = (unsigned long)0xc060;
    txdatabuf[1] = (unsigned long)0xffff;
    txdatabuf[2] = (unsigned long)0xB100;
    txdatabuf[3] = (unsigned long)0x0000;
    data_idx = 0;
    tempTxW = txdatabuf[data_idx];
    tempTxW |= 0x00FE0000L; //select cs0
    if(data_idx == CSIH0_NumOfData){
    tempTxW |= ((unsigned long)1L<<31);
    CSIH0TX0W = tempTxW;
    }while(data_idx < CSIH0_NumOfData);

    void CSIH0_Start(void){

    rx_ind = 0;
    EOT_flg = 0;

    // enable transmission and reception
    CSIH0.CTL0.UINT8 = 0xE0;

    CSIH0MRWP0 =
    //[31:23] reserved
    (0x0 <<16) //[22:16] read pointer of the receive buffer (not required in
    // tx-only buffer mode)
    //[15:7] reserved
    |(0x0); //[6:0] read/write pointer of the transmit buffer

    CSIH0MCTL2 =
    (0x1 <<31) //[31] start trigger for buffer transfer
    //[30:24] reserved
    |(CSIH0_NumOfData <<16)
    //[23:16] number of transfer data
    //[15:7] reserved
    |(0x00); //[6:0] start pointer of the transmit data


  • Hello Akshay

    Below is ftp link to download a sample project that demonstrates usage of the CSIH in master mode.

    It was tested on RH850/P1M-C device  ( 240MHz CPU clock ) but the CSIH is same for P1H-C.    

    Please have a look at this example. It should help you figure out your issue.


    Regards Dave 

     To download the file(s) please click on the respective link(s) below.

    Your password is: )a?|Cu/cyy

    Name: P1M-C_CSIH_TX_RX_INTERRUPT_DEMO_REV2_Installer.exe
    Size: 812.8 KiB
    Expires: July 29, 2021
    Download: https://filexchng.rea.renesas.com/download?domain=REA&id=20d6a699bc1648528ead9d9e26c4f14d-afca5f013b5e4916bfc4bad7db8db99c


  • Hello David

    Thanks for the driver regarding the clock the issue was from the hardware side so. now i am able to get the clock on the spi analyzer and MISO and MOSI lines are also showing proper data on the analyzer.

    Although, I had an issue that my miso lines show the data on the analyzer and my receive interrupt is also generated but when i read the data from the RX0W register or view the register from the debugger window it contains zeros i am not able to understand why it does not contain the data on the MISO pin? I am able to see that the TX0W is written properly.

    Am i doing something wrong while reading the RX0W register can you help me with this?



  • Hello Akshay

    I would close your debug window so you are not trying to read the CSIH receive register. Only use your embedded code for reading from the receive buffer. I am not sure this is your issue but I have seen problems where the debugger is reading peripheral status flags in a memory windows and clearing flags from the read operation and this cause conflicts with the users embedded sw.

    I would double check your port pin settings to confirm you have configured the CSIH SI pin correctly for CSIH SI functionality. 

    Regards Dave 

  • Hello David 

    Thanks for the reply, I have checked all the port pin setting and tx and rx part. I am using transmit only data buffer and sending 8bit data at a time. Total 64 bit i am sending and for each 8 bit sent i am receiving a receive interrupt. In receive Interrupt i am just reading the RX0W. But when i print these received values on the UART i can only see the chip select bits that  i configured and the data part is empty{i.e 0xfe0000}. Here i am using chip select 0 signal. 

    Also, when i check my spi analyser i can see all the signals are transmitted and received fine i.e. the MISO and MOSI lines contain data which i am expecting to read from RX0W. So, i have only one issue that why isn't my RX0W contain the MISO lines data whenever receive interrupt is generated?

    Can you guide me here because i am stuck on this point and i don't know how to move ahead with resolving the issue? Also, i have shared my code above if you want to have a look at the reception side.



  • Hello Akshay

    I reviewed your ports settings so I do not see a misconfiguration issue. I will have to review you code in more detail to see what is causing your issue.  Are you running this code on your own embedded target hw or a P1x-C PiggyBack Board ?  Are you sure you do not have some hw mistake in your design that is causing the MCU pin not to see the signal ?  Are you able to configure your MISO pin as a GPIO signal and have the MCU be able to read hi and lo signal values on P5_7 ?  This is assuming you have the ability to externally set this signal

    Regards Dave 

  • Hello David 

    So, I am using embedded target hw with P1HC and I have checked that when I set the P5_7 from the console it is reflected on the MISO pin so the lines are proper from HW side. I guess i am not reading the RX0W properly. Is there any other way to implement this?

    Regards Akshay

  • Hello David 

    So, I am using embedded target hw with P1HC and I have checked that when I set the P5_7 from the console it is reflected on the MISO pin so the lines are proper from HW side. I guess i am not reading the RX0W properly. Is there any other way to implement this?

    Regards Akshay

  • Hello Akshay

    I ran your code on my P1H-C 1372 device and the data reception is working as expected. I executed the 

    functionality in Akshaycode.c on my PiggyBack Board, externally looping CSIH0 SO and SI pins so whatever is transmitted should be received back.  In CSIH0_ExternalLoopbackTest.png you can see screenshots from GHS debugger where the data is received correctly.  Below is ftp link to download Akshay.zip which contains the source file and the png file.

    To download the file(s) please click on the respective link(s) below.

    Your password is: #f;3/|kq&]

    Name: Akshay.zip
    Size: 51.8 KiB
    Expires: July 24, 2021
    Max Downloads: 5
    Download: https://filexchng.rea.renesas.com/download?domain=REA&id=75c75a16e9834da986dc24c5e447412a-fe2d4cfbcdfa4981adaef6f353890f01

    Regards Dave 

  • Hello Dave 

    Thankyou for you support, I was able to establish my communication.

    Just wanted to know one more thing. I need to integrate a middleware RTOS layer for my project and I am currently using ghs multi as SDK. So, what are the steps to integrate RTOS over RH850 P1HC?

    I am trying to use OSEK OS for my project. Is it possible to integrate OSEK OS on P1HC and what is the procedure i must follow to at least run a single task on RH850?

    Also, suggest if any free RTOS we can use here and if any sample drivers are available for the same.



  • Most RH850/P1x applications are automotive and require AUTOSAR, which has to be purchased from 3rd party supplier.  You should investigate Vector, Elektrobit, etc. for such solutions.  There are no Renesas provided drivers for any free RTOS.

  • Hello Akshay

    As Jim stated there are many 3rd party OS vendors supporting RH850/P1H-C.  Each vendor has documentation detailing what is necessary for proper integration of their OS.

    There is FreeRTOS but you would have to port it specifically to P1H-C.  This is not something that is supported by Renesas.

    Below are some links about this activity someone did for a RH850. 



    In the future I suggest you start a new thread for new topics.


  • Hello Dave

    Thanks for the links and support for the RTOS. I was able to configure TOPPERS/OSEK kernel for my SoC. I need to configure CAN module also and i don't have a proper reference code for P1HC. And, I am trying with the UM but facing issue if you can help with the implementation procedure only for the loopback or even a sample driver for CAN would do.