SPI in Slave Mode with DMAC on RA4M2

Hi all,

I'm developing the SPI communication between two different Core, on my side the uController is the Slave and it have to process the signal with a transfer size of 2 bytes, the input signals are MOSI and RSPCK. On my ucontroller (RA4M2) all the peripherals runs at 32MHz and the RSPCK runs at 2.56MHz. So I have set the peripheral SPI0 in slave mode (clock synchronous operation) with the DMAC, the images below show the configuration done in the RASC tool and in the code for initialization and configuration of the peripherals:

         

The issue is that the DMAC is only able to process the first three halfwords received and therefore no further data will be processed by the DMAC.

The images below shown the signals captured from the oscilloscope. The yellow signals is the MOSI, the green is the RSPCK, the blue is a toggle that I put inside the function spi_tei_isr() to visualize the trigger on SPI_EVENT_TRANSFER_COMPLETE, the pink is a toggle  that I put inside the function spi_eri_isr() to visualize the error event. From the images is clear that there isn't any error event and SPI_EVENT_TRANSFER_COMPLETE triggered only two times. In the destination buffer the first three values are correctly copied from SPDR_HA, and the values saved are consistent with the signals captured from the oscilloscope.

                

 

My questions are:

  1. Are there any missing configurations to do for SPI or DMAC or interrupts?
  2. Is correct that SPI_EVENT_TRANSFER_COMPLETE trigger after three halfwords instead of one?
  3. Are there any issue in the FSP v3.0.0 for the peripheral that I use?
  4. Are there any example for this purpose?

In my code I use:

  1. ARM compiler v6.16
  2. Optimization level 3
  3. FSP v3.0.0

Thanks,
Paolo.

  • Hi PaoloG-

    I notice you have the interrupt priority for your interrupts set at 0. Have you tried with lower priority settings?

    I'm wondering if setting them at the highest priority level might be causing a problem. Normally I only use the highest level interrupt for system operations.

    Let me know what you think.

  • Hi WarrenM,

    I tried to set multiple values with a priority lower than 0, but there wasn't any changes, I got the same signals from the oscilloscope.

    Do you have any other suggestions?


    Thanks,
    Paolo.

  • Hi PaoloG-

    Which spi driver are you using? When I add a driver with r_spi or r_sci_spi in the FSP stack tab I only see the DTC as transfer driver options. Have you tried using the driver and the DTC instead of DMA?

    I'm selecting EK-RA4M2 as target with FSP 3.0.0.

  • I fixed the bug!

    From my point of view the bug is related to the trigger SPI_EVENT_TRANSFER_COMPLETE, because when I use the SPI0 with DMAC the trigger happens in the middle of the transmission so the function spi_tei_isr() will be called and in slave mode the SPI0 will be switched off even if the SPI0 isn't in idle mode. To fix the bug I done this:


    The images below shown the signals captured from the oscilloscope. The yellow signals is the MOSI, the green is the RSPCK, the purple is a toggle that I put inside the function spi_tei_isr() to visualize the trigger on SPI_EVENT_TRANSFER_COMPLETE, the pink is a toggle  that I put inside the function spi_eri_isr() to visualize the error event.

    This image shown a wrong transmission, because the trigger SPI_EVENT_TRANSFER_COMPLETE happens in the middle of the transmission and after that trigger the DMAC lost all the messages because the SPI is switched off.

    This images shown the transmission after the fix that I done. The trigger SPI_EVENT_TRANSFER_COMPLETE never happens and the DMAC process correctly all the messages from the SPI0.

    Note:
    I found also another way to process the SPI messages in RX instead of using DMAC or DTC and the management of the interrupts. Inside the function spi_rxi_isr() is called the function r_spi_receive() and if the parameters count, p_rx_data and bit_width of spi_instance_ctrl_t will be set, the SPI messagges will be stored directly from SPDR to p_rx_data. In this way I never lost any SPI messages, because the trigger SPI_EVENT_TRANSFER_COMPLETE happens at the end of the SPI communication (image below).

    Why there aren't informations in the UserManual of the uController or of the FSP about this modality?

    Best Regards,
    PaoloG.

  • Hi PaoloG-

    Thanx for letting us know what you found. I will pass this along to the development team to see what they think.

  • Hi All,

    I'm in the same scenario described in the previous messages and I'm using SPI with DMAC. I noticed that in some cases I have an overrun error message on the SPI if I set the optimization level to -O1, instead if I use the optimization level -O3 some messages are correctly recorded and for others I have the overrun error.

    I tried to speed up the clock of the DMAC and I tried to put at higher priority to the SPI and the DMAC, but I always have the same overrun error.

    How I can improve the performance of the DMAC also for the optimization level -O1?


    Regards,
    Paolo.