RAM ECC Test Feature


I'm having some trouble understanding the RH850 ECC test feature. Apparently we can enable it using LRTSTCTL.ECCTST, but what does LRTSTCTL.DATSEL do exactly? If we let it '0', does it mean that we can perform a RAM write to an address without a new ECC being generated, which would prompt an ECC error at read time?

And why do we need LRTDATBF0 if we don't know the checksum generation algorithm?



  • ECCTST allows the ECC bits to be read, and DATSEL determines whether you're writing to the data bits or ECC bits. Do you have the safety application note for your device? If not, please contact Renesas as there are preconditions for its provision.
  • In reply to Scott Winder:

    Thanks Scott. I just don't understand how writing to the data bits is a 'test' feature of the ECC. Isn't this a regular write to some RAM address? Will the ECC be disabled while writing, hence signaling an ECC error on reading?

    I don't have the safety application note, are its contents relevant for this issue?
  • In reply to swift:

    DATSEL allows you to write test patterns into RAM, and yes, it can be used to write data that will trigger an ECC error. The safety application note (SAN) describes this and other safety features in more detail.
  • In reply to Scott Winder:

    Dear Winder
    can you share an ECC source code which be implemented in some application.
  • Hello, can you please let me know about the algorithm used for ECC in Renesaus Rh850.