Interrupt redirection from boot loader to application


I am using the v850 processor in a project where we want to split the software into a boot loader part and a application part. With the help of the SelfLib library I have succeeded in creating a boot loader that is able to reprogram the application via UART. However, I have some problems with the redirection of interrupts from the boot loader to the application.

The interrupt table of the boot loader resides in the memory range 0x0 through 0x7cf. The application is programmed (using SelfLib) at addresses starting at 0x15000 and up. This means that the interrupt table of the application resides in the memory range 0x15000 through 0x157cf.

My first approach was to use the "br" instruction to branch directly from the boot loader to the corresponding interrupt handler of the application, i.e., (from startup.s)

.offset 0x02f0

  jr 0x15000

.offset 0x0320

  jr 0x15000

However, this did not work. The application runs for a while and then hangs. My second approach was to write interrupt wrappers that call the corresponding memory locations, i.e.,

.offset 0x02f0

  .extern _INTTT0CC1_APPL


.offset 0x0320

  .extern _INTTT1CC0_APPL


where the wrappers then was defined as

typedef void (*fnPtr)(void);

__interrupt void INTTT0CC1_APPL()


    ((fnPtr)(0x15000 | 0x2f0))();


__interrupt void INTTT1CC0_APPL()


    ((fnPtr)(0x15000 | 0x320))();


Using this approach the application runs but the performance is not as good as before the separation into a boot loader and an application part.

Any ideas and guidelines about how to achieve interrupt redirection from a boot loader to an application program would be very helpful for me.

Kind regards,


  • Anders,

    Sorry for the delay in aswering your request.  Perhaps you could provide details of which V850 device you are using.

    Some devices have an "Exception Handler Address Switching Function" as described in the user manual.  v850E2/Fx4 devices are an example device that provide this as an option (eg. FK4-2meg device with FlexRay: uPD70F4010).   Please reference section 6.4 of the document at this link (

    Older devices may require you to have the boot interrupt vector table located at address 0 select either the boot ISRs or the application vector table based on a flag that is at a fixed RAM address (or perhaps a dedicated general purpose register)

    Let us know if you have any questions,


  • Hello Gary,

    Thank you for your response. We are using the V850E/PHO3 (D70F3441F1) device and I do not know whether the functionality you are referring to is available.

    I found a note on the FAQ pages regarding interrupt redirection. There it was suggested to use an approach like the following (which I believe is what you are describing in the approach for older devices)

    .offset 0x02e0

      .extern _INTTT0CC0

      tst1 BITPOSITION, zdaoff(BITADDRESS)[zero]

      bz .+6

      jr 0x14ffa

      jr _INTTT0CC0


  • Anders,

    The PH03 is a V850E1 (V850E = V850E1) core.  It does not have the Exception Handler Address Switching Function I was mentioning.  That has been added in the V850E2 core.

    Yes, the example you found in the FAQ is what I was talking about.

  • Thank you for the info. Do you have any hints on how to use a dedicated register instead of a RAM address for distinguishing between boot load and application mode?


  • Anders,

    This is a compiler specific setting.  I am not sure which compiler you are using, but I will reference the GreenHills Software (GHS) compiler user manual (build_v800.pdf).  Please reference the GHS documentation for all notes and cautions related to using this option as other options you have set may restrict or conflict with the usage.


    Storing Global Variables in Registers

    Machine registers are primarily used by the compiler to store local variables or working values. This generally produces smaller and faster code than if most variables were on the stack. In certain circumstances, however, you can also allocate critical global data to registers (though this may decrease performance).  Unless you are building INTEGRITY code, you can reserve up to 5 global registers (r20 to r24 in that order).

    Specify the number of registers you want to reserve with the

    Target→Memory Models→Global Registers (-globalreg=n) option.


    Please mark this question as answered when you are satisfied.