Unable to trigger the Ethernet Interrupts.

Hello, 

I am using the RH850 P1M-C, and I am having problems using the Ethernet driver. The main problem is that the after the descriptors have been activated, I do not see any interrupts generated by the system. Attached is the register dump of the Ethernet after initialisation.

SFREthernet.txt
V850G3M, R7F701374
  G3M Core Registers
  FLXA0
  ETNA0
      EDSR0 = 00000003
      TDLAR0 = FEF00000
      TDFAR0 = FEF00000
      TDFXR0 = FEF000F0
      TDFFR0 = 00000001
      RDLAR0 = FEF00100
      RDFAR0 = FEF00100
      RDFXR0 = FEF001F0
      RDFFR0 = 00000001
      EDMR0 = 00000040
      EDTRR0 = 00000000
      EDRRR0 = 00000000
      EESR0 = 00000000
      EESIPR0 = 00240000
      TRSCER0 = 00000000
      RMFCR0 = 00000000
      FDR0 = 00000707
      RMCR0 = 00000000
      RPADIR0 = 00000000
      FCFTR0 = 001700E0
      TFSR0 = 02000000
      RFSR0 = 00000000
      ECMR0 = 0000006A
      RFLR0 = 0003FFFF
      ECSR0 = 00000000
      ECSIPR0 = 00000017
      PIR0 = 00000000
      PLSR0 = 00000000
      PIPR0 = 00000000
      APR0 = 0000FFFF
      MPR0 = 00000000
      PFTCR0 = 00000000
      PFRCR0 = 00000000
      TPAUSER0 = 0000FFFF
      TPFRCR0 = 00000000
      BCFRR0 = 00000000
      CRBCFRR0 = 00000000
      EMR0 = 00000000
      MAHR0 = 12345678
      MALR0 = 00009ABC
      TROCR0 = 00000000
      CDCR0 = 00000000
      LCCR0 = 00000000
      CEFCR0 = 00000000
      FRECR0 = 00000000
      TSFRCR0 = 00000000
      TLFRCR0 = 00000000
      RFCR0 = 00000000
      MAFCR0 = 00000000
      ARSTR = 00000000
      TSU_CTRST = 00000000
      TSU_FWSL0 = 00000000
      TSU_FWSL1 = 00000000
      TSU_FWSLC = 00000000
      TSU_FWSR = 00000000
      TSU_FWINMK = 00000000
      TSU_VTAG0 = 00000000
      TSU_VTAG1 = 00000000
      TSU_ADSBSY = 00000000
      TSU_TEN = 00000000
      TSU_POST1 = 00000000
      TSU_POST2 = 00000000
      TSU_POST3 = 00000000
      TSU_POST4 = 00000000
      TXNLCR0 = 00000000
      TXALCR0 = 00000000
      RXNLCR0 = 00000000
      RXALCR0 = 00000000
      TXNLCR1 = 00000000
      TXALCR1 = 00000000
      RXNLCR1 = 00000000
      RXALCR1 = 00000000
      TSU_ADRH0 = 00000000
      TSU_ADRL0 = 00000000
      TSU_ADRH1 = 00000000
      TSU_ADRL1 = 00000000
      TSU_ADRH2 = 00000000
      TSU_ADRL2 = 00000000
      TSU_ADRH3 = 00000000
      TSU_ADRL3 = 00000000
      TSU_ADRH4 = 00000000
      TSU_ADRL4 = 00000000
      TSU_ADRH5 = 00000000
      TSU_ADRL5 = 00000000
      TSU_ADRH6 = 00000000
      TSU_ADRL6 = 00000000
      TSU_ADRH7 = 00000000
      TSU_ADRL7 = 00000000
      TSU_ADRH8 = 00000000
      TSU_ADRL8 = 00000000
      TSU_ADRH9 = 00000000
      TSU_ADRL9 = 00000000
      TSU_ADRH10 = 00000000
      TSU_ADRL10 = 00000000
      TSU_ADRH11 = 00000000
      TSU_ADRL11 = 00000000
      TSU_ADRH12 = 00000000
      TSU_ADRL12 = 00000000
      TSU_ADRH13 = 00000000
      TSU_ADRL13 = 00000000
      TSU_ADRH14 = 00000000
      TSU_ADRL14 = 00000000
      TSU_ADRH15 = 00000000
      TSU_ADRL15 = 00000000
      TSU_ADRH16 = 00000000
      TSU_ADRL16 = 00000000
      TSU_ADRH17 = 00000000
      TSU_ADRL17 = 00000000
      TSU_ADRH18 = 00000000
      TSU_ADRL18 = 00000000
      TSU_ADRH19 = 00000000
      TSU_ADRL19 = 00000000
      TSU_ADRH20 = 00000000
      TSU_ADRL20 = 00000000
      TSU_ADRH21 = 00000000
      TSU_ADRL21 = 00000000
      TSU_ADRH22 = 00000000
      TSU_ADRL22 = 00000000
      TSU_ADRH23 = 00000000
      TSU_ADRL23 = 00000000
      TSU_ADRH24 = 00000000
      TSU_ADRL24 = 00000000
      TSU_ADRH25 = 00000000
      TSU_ADRL25 = 00000000
      TSU_ADRH26 = 00000000
      TSU_ADRL26 = 00000000
      TSU_ADRH27 = 00000000
      TSU_ADRL27 = 00000000
      TSU_ADRH28 = 00000000
      TSU_ADRL28 = 00000000
      TSU_ADRH29 = 00000000
      TSU_ADRL29 = 00000000
      TSU_ADRH30 = 00000000
      TSU_ADRL30 = 00000000
      TSU_ADRH31 = 00000000
      TSU_ADRL31 = 00000000
      HDMMDR0 = 00000000
      HDMISR0 = 00000000
      HDMIER0 = 00848F01
  _Others
  FLMD
  FACI0
  FACI1
  DNFA2
  DNFA3
  DNFA4
  DNFA5
  DNFA6
  DNFA7
  FCLA0
  FCLA1
  FCLA2
  FCLA3
  FCLA4
  FCLA5
  FCLA6
  FSGD5A
  ERRSLV5A
  FSGD5B
  ERRSLV5B
  FSGD5C
  ERRSLV5C
  FSGD5D
  ERRSLV5D
  ERRSLV5AI
  ERRSLV5BI
  ERRSLVDG0
  ERRSLVDG1
  ECCCSIH0
  ECCCSIH2
  ECCTTCAN0
  ECCMCAN1
  ECCFLX0
  ECCFLX0T0
  ECCFLX0T1
  ECCCSIH1
  ECCCSIH3
  ECCMCAN0
  CSIH1
  PMMA1
  CSIH3
  PMMA3
  HSUS1
  RLN31
  RSENT0
  RSENT1
  RSENT2
  RSENT3
  RSENT4
  RSENT5
  RSENT6
  SINT
  MTTCAN0
  MCAN1
  DCRB0
  DCRB2
  ECMM0
  ECMC0
  ECM0
  PIC2C
  CSIH0
  PMMA0
  CSIH2
  PMMA2
  HSUS0
  RLN30
  STM0
  FSGD2A
  ERRSLV2
  ERRSLV2AI
  GTM0
  ECCGTM0
  ECCGTM1
  ECCGTM2
  ECCGTM3
  WDTA0
  SWD0
  FSGD1A
  ERRSLV1
  FSGD1B
  ERRSLV1AI
  MCAN0
  DCRB1
  DCRB3
  CLMA0
  CLMA1
  CLMA2
  CLMA3
  CLMA5
  FSGD4A
  ERRSLV4
  FSGD4B
  FSGD4C
  ERRSLV4C
  ERRSLV4AI
  ADCF0
  ADCF1
  OTS0
  FSGD3A
  ERRSLV3
  FSGD3B
  ERRSLV3AI
  NTU0
  FSGDF0
  ERRSLVF0
  FSGDE0
  ERRSLVE0
  ERRSLVFI
  ERRSLVEI
  ERRSLVMI
  ERRSLVHI
  ERRSLVXI
  HSSPID
  HTHDMA
  IPG
  PEG
  SEG

After this just the TRR bits are set to enable the DMA to transmit the data. What I notice that none of the interrupts get triggered. Does anyone have any suggestions regarding this?