Differential ADC on RA6M3

I have a few questions regarding differential ADC.

The ADC12 block diagram in the RA6M3 user's manual shows the differential signal path going through the programmable gain amplifier. Does that mean I must enable the amplifier by setting the P00xENAMP bit in the ADPGACR register even if I don't want to enable the gain setting (P00xGEN = 0 and P00xDEN = 0)?

The ADPGACR P00xSEL0 and P00xSEL1 bits seem redundant and could lead to problems if both were enabled. SEL0 sends the signal in a path bypassing the PGA amplifier, while SEL1 sends the signal in a path through the PGA amplifier. It seems like there would be problems if both bits were set at the same time. I'm asking not because I want to do that, but to see if my understanding of the SEL bits is correct.

The RA6M3 datasheet specifies a "Dynamic range" in Table 2.40. This applies to channels AN000 to AN002 when dedicated sample-and-hold is in use. The minimum is 0.25V and the max is VREFH0 - 0.25V. I just want to confirm this limit only applies when dedicated sample-and-hold is in use and not when PAG is enabled to support differential input.

How does the RA6M3 cope with negative differential voltages (input signal is less than the PGAVSS000 reference voltage)? Is the value in the ADDR register treated as a signed value or will ADDR be 0?

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  • I heard back in response to my support ticket. Here's the response:

    You must enable the PGA to use the differential inputs.  Note that AN0,AN1and AN2 all share the differential input PGAVS000.

    To use the differential input you must also set the P00xSEL0 = 0, P00xSEL1 = 1, P00xENAMP = 1 and P00xGEN = 1.  

     

    The P00xSEL1 and bit is also used to connect the PGA to the ACMPHS high speed comparator while disconnecting the PGA from the ADC.

     

    The dynamic range specification is only when the channel dedicated S/H is used.

     

    The PGA gain is Gain*(Vin - Vs) +0.5 * AVCC

    For a 12 bit result register, when Vin=Vs the output of the PGA is at  1/2 AVCC which would read 0x800 .

    When Vin > Vs, the readings will go from 0x800 to 0xFFF.

    When Vin < Vs, the reading will go from 0x800 to 0x000.

    When I asked specifically about setting SEL0 = 1 and SEL1 = 1 at the same time:

    Do not set P00xSEL0 and P00xSEL1 to 1 as this will connect both the input pin and the output of the PGA to the ADC at the same time!

Reply
  • I heard back in response to my support ticket. Here's the response:

    You must enable the PGA to use the differential inputs.  Note that AN0,AN1and AN2 all share the differential input PGAVS000.

    To use the differential input you must also set the P00xSEL0 = 0, P00xSEL1 = 1, P00xENAMP = 1 and P00xGEN = 1.  

     

    The P00xSEL1 and bit is also used to connect the PGA to the ACMPHS high speed comparator while disconnecting the PGA from the ADC.

     

    The dynamic range specification is only when the channel dedicated S/H is used.

     

    The PGA gain is Gain*(Vin - Vs) +0.5 * AVCC

    For a 12 bit result register, when Vin=Vs the output of the PGA is at  1/2 AVCC which would read 0x800 .

    When Vin > Vs, the readings will go from 0x800 to 0xFFF.

    When Vin < Vs, the reading will go from 0x800 to 0x000.

    When I asked specifically about setting SEL0 = 1 and SEL1 = 1 at the same time:

    Do not set P00xSEL0 and P00xSEL1 to 1 as this will connect both the input pin and the output of the PGA to the ADC at the same time!

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