I have a few questions regarding differential ADC.
The ADC12 block diagram in the RA6M3 user's manual shows the differential signal path going through the programmable gain amplifier. Does that mean I must enable the amplifier by setting the P00xENAMP bit in the ADPGACR register even if I don't want to enable the gain setting (P00xGEN = 0 and P00xDEN = 0)?
The ADPGACR P00xSEL0 and P00xSEL1 bits seem redundant and could lead to problems if both were enabled. SEL0 sends the signal in a path bypassing the PGA amplifier, while SEL1 sends the signal in a path through the PGA amplifier. It seems like there would be problems if both bits were set at the same time. I'm asking not because I want to do that, but to see if my understanding of the SEL bits is correct.
The RA6M3 datasheet specifies a "Dynamic range" in Table 2.40. This applies to channels AN000 to AN002 when dedicated sample-and-hold is in use. The minimum is 0.25V and the max is VREFH0 - 0.25V. I just want to confirm this limit only applies when dedicated sample-and-hold is in use and not when PAG is enabled to support differential input.
How does the RA6M3 cope with negative differential voltages (input signal is less than the PGAVSS000 reference voltage)? Is the value in the ADDR register treated as a signed value or will ADDR be 0?
Thanks for your reply. The dynamic range is a bit of a mystery. There are four operating conditions that relate to ADC error in the datasheet:
I heard back in response to my support ticket. Here's the response:
You must enable the PGA to use the differential inputs. Note that AN0,AN1and AN2 all share the differential input PGAVS000.
As I was reviewing this, I think the variety and spec-based nature of these questions would actually be best served by submitting a ticket to technical support. They would be able to get the electrical characteristics and other information as needed. Thank you!
If this, or any other response, answers your question, please mark it as a verified answer. Thank you!
RenesasRulz Forum Moderator
I've got the understanding of the table 2.40 that the minimum of 0.25V and maximum of VREFH0-0.25V means that this must be the range for the quoted (better) specifications to be met with sample-and-hold in place, and that a signal level outside this range are according to the specification when no sample-and-hold is enabled. I.e. it will not damage anything. Please correct me if I'm wrong. I got the information from https://renesasrulz.com/embedded-system-platform/synergy/f/forum/14653/s5d3-adc - but it is a different product.I'm interested in the reply to the setting of P00xSEL0 and P00xSEL1, as you do have a point that it seems confusing and troublesome that both can be enabled, so following this thread.
The dynamic range characteristic is only found in #2. I would have expected them to also provided guaranteed error ranges for inputs outside the dynamic range if it were just a matter of it being more accurate within the dynamic range and less accurate outside the dynamic range. In any case, it isn't really clear why they are providing the dynamic range constraint.
I have created a support ticket. I will follow up with their response, if they don't respond here directly.
To use the differential input you must also set the P00xSEL0 = 0, P00xSEL1 = 1, P00xENAMP = 1 and P00xGEN = 1.
The P00xSEL1 and bit is also used to connect the PGA to the ACMPHS high speed comparator while disconnecting the PGA from the ADC.
The dynamic range specification is only when the channel dedicated S/H is used.
The PGA gain is Gain*(Vin - Vs) +0.5 * AVCC
For a 12 bit result register, when Vin=Vs the output of the PGA is at 1/2 AVCC which would read 0x800 .
When Vin > Vs, the readings will go from 0x800 to 0xFFF.
When Vin < Vs, the reading will go from 0x800 to 0x000.
When I asked specifically about setting SEL0 = 1 and SEL1 = 1 at the same time:
Do not set P00xSEL0 and P00xSEL1 to 1 as this will connect both the input pin and the output of the PGA to the ADC at the same time!