Interrupt calling from HEW

Hello All,

 

My problem statement = How to call ISR function automatically when interrupt will get generated ( in HEW) ?

As per knowledge, In HEW, there is "intprg.c". This .c contains all the functions with interrupt name. 

and in "vecttbl.c" , there is a function pointer named "void (*INT_Vectors[])(void)". and this function body contains address of all the functions which are present in "intprg.c".

 

So, I have called my "CAN_Ch_1_TX_ISR()" in interrupt function present in ""intprg.c".

 

So I enabled all interrupts in code. but when interrupt is generated, "CAN_Ch_1_TX_ISR()" not gets called automatically?

 

Is there any HEW setting needed to do for this?

Parents
  • Thank you Paul and FrankL.

    I am using Renesas c/c++ compiler.

    Its true that hardware automatically calls ISR function. But how hardware will detect which function to call as ISR for a particular interrupt?
  • The compiler is for H8/SH/M16C/RX ?
    In the processor the interrupt request bits for the different peripheral functions are hard-wired to corresponding interrupt vector. If a specific interrupt request is triggered the interrupt controller checks if the interrupt is enabled. If so it reads the corresponding entry from the vector table.
    The device hardware manual shows which interrupt vector corresponds to which interrupt cause.
  • Hi FranKl

    I am using SH compiler.
    In manual , they have given table which indicates which "interrupt" will get generated based on which "interrupt flag".

    as per that , I have unmasked corresponding Interrupt in hardware register.
    during debugging, its found that "interrupt flags" are getting updated.

    But my question is how does hardware detects which function to call based on interrupt?
    Do I need to connect my ISR_FUN() to corresponding vector address?
  • Hi FranKL
    Thank you for your help.
    I have already checked HW manual. But will go through it again.
    But If you found my question or my understanding wrong, then plz correct me.
  • Which SH processor do you use?
    For example SH-2 and SH-2A processors have a hardware interrupt controller. This checks ALL interrupt requests after every instruction. If it finds an active interrupt AND interrupts are enabled it will trigger the interrupt routine.
    SH-4 or SH-4A do NOT have an interrupt controller. There ALL interrupts trigger the same interrupt handler. This has to determine what the interrupt cause is by software and call the interrupt routine.

  • I am using sh2A processor.
    I have unmasked interrupt using IMR register of sh72531.
    And also set highest priority to interrupt using IPR register of "Interrupt controller"
    sh72531 has HW interrupt controller
Reply Children
  • And you have changed the Interrupt Mask Level in bit 4-7 of PSR, preferably set to 0000?
  • There is no such PSR register in sh72531.

    registers related to CAN inetrrupt and Interrupt controller are (from sh72531) =

    IMR = mask/unmask CAN tx/rx interrupts
    MBIMR = enable/disable Mailbox interrupt after tx/rx
    IPR28 = CAN interrupt priority status register
  • there is Interrupt priority set register where all bits are 0 during power on reset. but if priority is 0, then all interrupt like ADC,timer,CAN etc are masked (even if you have configured peripheral interrupt mask register to unmask that interrupt).
    So, as per datasheet of sh72531, we can give priority between 0 to 15(15 is highest pri.)So I have given 15th priority to CAN, but still its not calling ISR.
  • OK, in SH72531 manual it is called only SR (Status Register) instead of PSR (Processor Status Register). It is a CPU control register.

  • when I run code on hardware and debug it, then its observed that "Interrupt flag" keeps updating as per code, but based on value change in "interrupt flag",interrupt is not generated(even if interrupt is unmaksed.). I applied breakpoint to my ISR function, but its not get called.

    Can transmission interrupt related things from sh72531 =

    1) IRR8 bit from IRR register = it becomes 1 when data from mailbox is transmitted.
    2) IMR8 bit from IMR register = used to mask / unmask interrupt generation from IMR8 (0 = unmask; 1 = mask)
    3) MBIMR1 = enable/disable updation of IRR8 bit for MB31 to 16.
    4) IPR28 (from INTC chapter of sh72531) = it sets priority of IRR8 interrupt for CAN channel A. I have selected highest pri = 1111.
  • Is any #pragma setting need to do for interrupt handler?

    My code setting = (Setting regarding interrupt)

    IMR = 0xFEFD = tx/rx inetrrupt enable
    MBIMR1 = 0x7FFF = tx interrupt enabled
    IPR28 = 0xF000;(priority for CAN Ch-A