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Interrupt enable and disable details

Hi ,

below shown details,as it helps to disable or enable interrupt ? or what is this macro function,please let me know what this function?

S7G2

e2 studio

this details placed in bsp_common.h

  • Short answer, yes, it is disabling the interrupts.

    Longer answer:

    Interrupts have priority levels.  There is a priority number which is a different size on different Arm-based silicon.  This is the meaning of the macro NViC_PriorityBits.  A lower level number has a higher priority than a higher level number. 

    The NVIC that masks (ignores) all interrupts with a lower priority (higher level number) than specified in the Base Priority register.  When the base priority is at it's highest numerical value, all interrupts are allowed.

    So decreasing the value of the base priority effectively disables interrupt sources with a higher priority level.

    The macro in question disables all interrupts with a priority level number higher than BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION but still allows higher priority (lower level number) interrupts to be processed.

  • Good explaination here on int processing on the Cortex M chips. The difference between the low end M0's and the M4 chips usually involves a simplifed interrupt priority scheme, with the M0 having a smaller register for the priorities and fewer levels.

    interrupt.memfault.com/.../arm-cortex-m-exceptions-and-nvic