For more than two decades now, we've had a continuing debate on the two primary microprocessor architecture philosophies. There continue to be successful products that use both CISC (Complex Instruction Set Computer) and RISC (Reduced Instruction Set Computer) architectures. The fact is, the best processor designs take the best of RISC and CISC and combine them in a hybrid microarchitecture.
The RISC vs CISC debate really heated up back in late 80's. The RISC camp believed that the instruction decoder was growing so complex in CISC processors, that the CISC designs didn't optimally use the available transistors. Moreover, CISC designs used microcode to handle the complex instructions. So many CISC instructions required multiple CPU clock cycles to complete.
The RISC advocates pushed a design that separated data access and math and logic instructions. The so-called load/store architectures dedicated instructions to move data between registers and memory. The logic and math instructions only operated on data in registers. The result was an architecture that could execute an instruction each clock cycle with an instruction decoder that was implemented with hard-wired logic rather than microcode.
The primary RISC contenders were the MIPS and Sun SPARC architectures. Proponents believed those processors would quickly usurp the Intel x86 architecture. We all know what happened. Moore's Law allowed Intel to continue along the CISC path and retake a leadership position in terms of processor performance.
What many people don't realize is that Intel turned to a hybrid RISC-CISC approach. The company developed an instruction decoder that broke complex instructions into simple microinstructions.
How does this tale apply to microcontrollers you ask? Well the RISC push came to microcontrollers much later. Looking back, the mission in the microcontroller space was focused more on integrating peripherals and targeting specific applications than on microarchitecture performance.
Today, however, microcontrollers are taking on increasing complex, performance-intensive tasks. Performance really matters. And a number of companies have turned to RISC architectures to try and boost performance.
Renesas has a long history with both RISC and CISC architectures. The company's H8 family is RISC based while the M16 and R32 families are CISC based. That background provided the Renesas RX microarchitecture design team with the skills needed to develop the ideal hybrid architecture.
The RX is primarily a CISC architecture that delivers significant advantages over RISC designs in terms of code density and therefore memory size requirements. But the RX also utilizes a five-stage pipeline and out-of-order instruction execution to deliver the goal of one instruction executed per clock cycle. The result is performance that bests the competitive RISC microcontrollers.
In a future post, we'll dig deeper into the subjects of code density and performance. We'll examine some real-world benchmarks and examples that explicitly show the advantages of the hybrid approach.
Anonymous
  • Calvin Grier Apr 14, 2010 6:56 AM

    Don't forget all the embedded RISC cores that didn't make it like M-core, Alpha, Motorola PowerPC, and maybe CoolRISC (or is that one still around?).

    What's also interesting is that some 8 bit RISC chips I've used, actually didn't make it to one-instruction per cycle on all of the operations. RISC chips with loads of op-codes start looking more like CISC anyway - which makes us wonder how they can call them RISC.

    Gotta love the hybrids. I wonder if any Hybrid cars are using hybrid MCUs.