I am pretty new to Renesas MCUs and problem can be really simple. But spent already whole day searching for answer wihtout success, so it is time to ask.

I am trying to speak with OLED screen on 4-wire SPI connected to UART3 (p4_1 and p4_3) on R5F64112DFB (100pin pkg). Whatever I do, I do not see CLK on oscilloscope. DATA runs fine.

I think I included all relevand code here:

#include "sfr111.h"
#include "rskr32c118def.h"
#include "main_serial_spi.h"

void main(void)               
{
    unsigned char ucLoopcnt;
    SPI_Master_init();
   
    while (1) {
            while(ti_u3c1 == 0)    {}             
            u3tb = 0x55;
    }
}        

// Port direction arguments
#define PDIR_INPUT    (0)
#define PDIR_OUTPUT    (1)

// Port for SPI clock
#define P_SPI_CLK    p4_1

// Port function select registers
#define PF_SPI_CLK    p4_1s
#define PF_SPI_DATA p4_3s

// Por function arguments
#define PF_SPI        3

void SPI_Master_init(void)
{
    /* CLK3    */
    pd4_1 = PDIR_OUTPUT;   
    PF_SPI_CLK = PF_SPI;
   
    /* TXD3 */
    pd4_3 =  PDIR_OUTPUT;
    PF_SPI_DATA = PF_SPI;

    smd0_u3mr    = 1; // \
    smd1_u3mr    = 0; //  > Synchronous Serial More
    smd2_u3mr    = 0; // /
    ckdir_u3mr    = 0; // internal clock , 243
    stps_u3mr    = 0; // 0 required on page 258, 243
    pry_u3mr    = 0; // 0 required on page 258, 243
    prye_u3mr    = 0; // 0 required on page 258, 243
    iopol_u3mr    = 0; // 0 required on page 258, 243
   
    clk0_u3c0    = 0; // \ Clock source f1 for u3brg
    clk1_u3c0    = 0; // /
    // bit2 missing (page 258)
    txept_u3c0    = 0; // Transmit register empty flag (page ?)
    crd_u3c0    = 1; // CTS disabled when 1(page 245)
    nch_u3c0    = 0; // Output mode "push-pull" for TXD and CLOCK pin (page 245)
    ckpol_u3c0    = 0; // Polarity (page?)
    uform_u3c0    = 1; // MSB first (page 245)
   
    te_u3c1        = 1; // Transmission enabled (page 258, 247)
    ti_u3c1        = 0; // Must be 0 to send or receive
    re_u3c1        = 0; // Reception is disabled when 0 (page 247)
    ri_u3c1        = 0; // Receive complete flag - U3RB is empty. (page 247)
    u3irs_u3c1    = 0; // 1 when transmission is completed, U3TB is empty. (page 247)
    u3rrm_u3c1    = 0; // Continuous receive mode off
    u3lch_u3c1    = 0; // Logical inversion off (page 258)
    // bit 7 missing (page 258)

    u3smr = 0x00; // Set 0 (page 258)
    u3smr2 = 0x00; // Set 0 (page 258)

    sse_u3smr3    = 0; // SS is disabled when 0 (page 251)
    ckph_u3smr3    = 0; // Non clock delayed (page 251)
    dinc_u3smr3    = 0; // Master mode when 0 (page 251)
    nodc_u3smr3    = 0; // Select a clock output mode "push-pull" when 0 (page 258, 251)
    err_u3smr3    = 0; // Error flag, no error when 0 (page 251)
    dl0_u3smr3    = 0; // Set 0 for no delay (page 251)
    dl1_u3smr3    = 0; // Set 0 for no delay (page 251)
    dl2_u3smr3    = 0; // Set 0 for no delay (page 251)
   
    u3smr4 = 0x00; // Set 0 (page 258)
   
    // u3c0 must be set before this function
    u3brg = (unsigned char)(((f1_CLK_SPEED)/(2*BIT_RATE))-1);
   
    DISABLE_IRQ;
    s3tic = 0b00000011;
    ENABLE_IRQ;
}

#pragma interrupt    _uart3_trans(vect=35)
void _uart3_trans(void)
{
    ir_s3tic = 0;
}