QSPI NOR Flash - Custom S7G2 board

We are having some issues with QSPI NOR Flash chip MT25QL256ABA1EW7 on our custom S7G2 board. It just errors with "SSP_ERR_UNSUPPORTED" on the open call.
We have tested the same code on Dev board (S7G2-DK) and it works just fine but the Dev board has different chip N25Q256A.
I know that the NOR Flash chip on S7G2-DK is getting obsolete and it was recommended to go with MT25QL256ABA1EW7 chip by micron/Renesas forums for new designs.
I just wanted to check and see if any one has any pointers for this issue.

I have tried the following as suggested from Synergy forum threads:

1. Modify BSP "bsp_qspi" to hardcode the manufacturer ID, Type, and capacity of the MT25QL256ABA1EW7 flash chip - no luck

2. Check if the chip is getting power supply - passed

SSP Version 1.1.3

e2 Studio Version 5.4.0.015


Thanks.

  • Hello Sam,

    Can you detail how did you modify the bsp_qspi files? These file are auto-generated by the Synergy Configuration which means that if the file was not saved and set to read-only, the changes you've made were removed and original file was restored.

    Regards
  • In reply to Renesas Karol:

    Right....so
    1. Before I made changes to that file, I did mark that file as read+write by right-clicking and going into properties
    2. Then.. I made changes, and saved them.
    3. Changed the file properties back to read only.
    4. re-compiled the project, checked the file again, and my changes were taken for that file.

    Thanks.
  • In reply to Sam:

    Hi Sam,

    There might be more changes between these chips, I suggest reading renesasrulz.com/.../s7g2-qspi-mt25ql256-work-only-one-time and all referred documents from chip's manufacturer.

    Regards,
    adboc
  • In reply to adboc:

    Hi Adboc,

    Thanks for your suggestions. I will check with the chip manufacturer as well. But attached is the waveform of Chip select and Clock lines from S7G2 to the MT25QL256ABA1EW7  chip. I am thinking the hardware interface between the S7G2 and the Flash chip is OK. It might be the BSP to support this chip?

     

    CS line probe on MT25QL256ABA1EW7 chip:

      

     

    CLK line probe on MT25QL256ABA1EW7 chip:

     

  • In reply to Sam:

    Hi Sam,

    User TLHQ wrote he had to modify some QSPI commands and had to disable XIP mode at startup (renesasrulz.com/.../32040. I suppose MTxx chips should work as well as NTxx chips, but there must be some differences in initialization and configuration procedures.

    Regards,
    adboc
  • Working on the same thing currently. If I figure it out, I'll let you know
  • In reply to Jake:

    Please see my post that explains the issue with the MT25Q here:

    I've also written code to take the device out of DTR mode and resets the non-volatile configuration to factory default - you  have to power cycle the part after executing the code to force the QSPI to reload the configuration NVM.

    To use code, change the #defines for your QSPI interface on your board.

    -Gary

  • In reply to garyj:

    Looks like the attachment was lost - here's the QSPI Recovery code"\:

    #define SEL IOPORT_PORT_02_PIN_07
    #define CLK IOPORT_PORT_02_PIN_14
    #define DQ0 IOPORT_PORT_02_PIN_11
    #define DQ1 IOPORT_PORT_02_PIN_10

    void ResetQSPI_NVM(void);

    void ResetQSPI_NVM(void)
    {
    const uint8_t nvm_write_enable=0x06;
    const uint8_t nvm_cfg_reg = 0xB1;
    uint16_t mask;
    ioport_level_t data_bit;
    ioport_level_t clk_bit;

    int i;

    g_ioport.p_api->pinCfg(SEL, IOPORT_CFG_PORT_DIRECTION_OUTPUT|IOPORT_CFG_PORT_OUTPUT_HIGH|IOPORT_CFG_DRIVE_HIGH); // SEL
    g_ioport.p_api->pinCfg(CLK, IOPORT_CFG_PORT_DIRECTION_OUTPUT|IOPORT_CFG_PORT_OUTPUT_LOW|IOPORT_CFG_DRIVE_HIGH); // Clock
    g_ioport.p_api->pinCfg(DQ0, IOPORT_CFG_PORT_DIRECTION_OUTPUT|IOPORT_CFG_PORT_OUTPUT_HIGH|IOPORT_CFG_DRIVE_HIGH); // DQ0 (command)
    g_ioport.p_api->pinCfg(DQ1, IOPORT_CFG_PORT_DIRECTION_OUTPUT|IOPORT_CFG_PORT_OUTPUT_HIGH|IOPORT_CFG_DRIVE_HIGH); // DQ1 (data)

    /* Send out the write enable for the non-volatile NVM command */
    g_ioport.p_api->pinWrite(CLK, IOPORT_LEVEL_LOW);
    g_ioport.p_api->pinWrite(SEL, IOPORT_LEVEL_LOW);
    g_ioport.p_api->pinWrite(DQ1, IOPORT_LEVEL_HIGH);
    for (mask = 0x80, clk_bit = IOPORT_LEVEL_LOW; mask!=0; mask = mask>>1) // mask will shift from MSB to LSB
    {
    if (mask&nvm_write_enable)
    data_bit = IOPORT_LEVEL_HIGH;
    else
    data_bit = IOPORT_LEVEL_LOW;

    g_ioport.p_api->pinWrite(DQ0, data_bit);
    clk_bit = !clk_bit;
    g_ioport.p_api->pinWrite(CLK,clk_bit);
    R_BSP_SoftwareDelay(20,BSP_DELAY_UNITS_MICROSECONDS);
    }
    g_ioport.p_api->pinWrite(SEL, IOPORT_LEVEL_HIGH);
    R_BSP_SoftwareDelay(100,BSP_DELAY_UNITS_MICROSECONDS);

    /* Send out the non-volatile NVM Write command */
    g_ioport.p_api->pinWrite(CLK, IOPORT_LEVEL_LOW);
    g_ioport.p_api->pinWrite(SEL, IOPORT_LEVEL_LOW);
    g_ioport.p_api->pinWrite(DQ1, IOPORT_LEVEL_HIGH);
    for (mask = 0x80, clk_bit = IOPORT_LEVEL_LOW; mask!=0; mask = mask>>1) // mask will shift from MSB to LSB
    {
    if (mask&nvm_cfg_reg)
    data_bit = IOPORT_LEVEL_HIGH;
    else
    data_bit = IOPORT_LEVEL_LOW;

    g_ioport.p_api->pinWrite(DQ0, data_bit);
    clk_bit = !clk_bit;
    g_ioport.p_api->pinWrite(CLK,clk_bit);
    R_BSP_SoftwareDelay(20,BSP_DELAY_UNITS_MICROSECONDS);
    }
    /* Send out the non-volatile NVM Write data */
    data_bit = IOPORT_LEVEL_HIGH;
    for (mask = 0x8000; mask!=0; mask= mask>>1) // mask will shift from MSB to LSB
    {
    g_ioport.p_api->pinWrite(DQ0, data_bit);
    clk_bit = !clk_bit;
    g_ioport.p_api->pinWrite(CLK,clk_bit);
    R_BSP_SoftwareDelay(20,BSP_DELAY_UNITS_MICROSECONDS);
    }

    g_ioport.p_api->pinWrite(SEL, IOPORT_LEVEL_HIGH);
    }
  • In reply to garyj:

    Awesome! Thanks a ton . hope it works!
  • In reply to garyj:

    Hi garyj,

    We have been trying to take the MT25QL256A device out of DTR mode by putting your code, it is not working. When I read device characteristics all I get is FF. We checked clock and data line by probing, it looks okay.

    Did you test this code with your hardware, are you able to come out of DTR mode by putting above code?

    SSP Version-1.3.0
    Board-S7G2-DK
    e2 studio Version: 5.4.0.018

    Thanks.
  • In reply to garyj:

    Hi garyj,

    Now we are able to come out of DTR mode by putting your code, earlier we were doing mistake.

    Thanks.
  • In reply to garyj:

    From where in the code do we call this function?