Upon reflection of the timing and setup requirements for the m32c/87 microprocessor-mode READY signal, I find something amusing.  The READY setup time is spec'd at a minimum of 26 nS.  However, at 32 MHz the nWR pulse (at zero wait states) is only 15 nS wide.  Thus, it's impossible to assert READY based on the nWR timing - you'd have to have future-predicting hardware to get the setup times right.  The only options I see are to either add a wait state (which increases read time too), or *always* keep READY low, and only make it high when you want to let the m32c continue, which means it's impossible to get zero wait state writes.

Anyone else notice this?  What techniques to you use to trigger/manage the READY signal?